參數(shù)資料
型號(hào): PE42632DTI
廠商: PEREGRINE SEMICONDUCTOR CORP
元件分類: 開關(guān)
英文描述: SP6T UltraCMOS 2.70 V Switch 100 - 3000 MHz,50ohm
中文描述: 100 MHz - 3000 MHz RF/MICROWAVE SGL POLE SIX THROW SWITCH, 1.15 dB INSERTION LOSS
封裝: ROHS COMPLIANT, FLIP CHIP-16
文件頁數(shù): 3/4頁
文件大?。?/td> 126K
代理商: PE42632DTI
Product Brief
PE42632
Page 3 of 4
Document No. 70-0226-01
│ www.psemi.com
2007 Peregrine Semiconductor Corp. All rights reserved.
Contact sales@psemi.com for full version of datasheet
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
Table 5. Truth Table
Table 6. Ordering Information
Table 4. Pin Descriptions
Figure 4. Pad Configuration (Top View)
Path
V3
V2
V1
ANT - TX1
0
1
ANT - TX2
0
1
ANT – RX1
1
0
ANT – RX2
0
1
0
ANT – RX3
1
0
ANT – RX4
0
8
7
5
6
11
13
2
14
10
3
9
4
1
12
15
16
TX1
GND
TX2
RX1
VDD
V1
V2
V3
GND
RX4
RX3
RX2
GND
GND ANT
PE42632 Die
Pin No.
Pin Name
Description
1
TX18
RF I/O – TX1
2
GND
TX Ground
3
TX28
RF I/O – TX2
4
RX18
RF I/O – RX1
5
RX28
RF I/O – RX2
6
RX38
RF I/O – RX3
7
RX48
RF I/O – RX4
8
GND
RX Ground
9
V3
Switch control input, CMOS logic level
10
V2
Switch control input, CMOS logic level
11
V1
Switch control input, CMOS logic level
12
VDD
Supply
13
GND
DC Ground
14
ANT8
RF Common - Antenna
15
GND
DC Ground
16
GND
DC Ground
Note:
8. Blocking capacitors needed only when non-zero DC
voltage present
Order Code
Description
Package
Shipping Method
PE42632DTI
PE42632-DIE-D
Bumped Wafer on Film Frame
Wafer (Gross Die / Wafer Quantity)
PE42632DBI
PE42632-DIE-400G
Die in Waffle Pack
400 Dice / Waffle Pack
EK-42632-01
PE42632-DIE-1H
Evaluation Kit
1/ box
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