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參數(shù)資料
| 型號： | PE7620DYEF-FREQ |
| 廠商： | PLETRONICS INC |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 40 MHz - 250 MHz, PECL OUTPUT |
| 封裝： | LEADLESS PACKAGE-6 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 119K |
| 代理商： | PE7620DYEF-FREQ |
Mar 2004
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com
6
Pl tronics, Inc.
PECL and LVDS Layout Guidelines
Pl tronics, Inc.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA
Manufacturer of High Quality Frequency Control Products
.
TOP SIDE
BYPASS
BOTTOM
SIDE
BYPASS
MULTI
LAYER
BYPASS
0.055
(1.4)
0.100
(2.54)
0.200 (5.08)
0 .185
(4.7)
0 .087
(2.2)
Solder Pad Layout which
accommodates all PECL surface mount
devices
'B Pkg'
5 x7
SUGGESTED PCB LAYOUTS
The output line should be designed with proper characteristic
impedance. Pletronics recommends laying out for the larger
'B package' with pads long enough to accept the smaller
5 x 7mm device. This permits the best option for alternate
sources of device. Pletronics also recommends connecting
Pin 1 and Pin 2 together on the models with
Q & QN OUT on pins 4 & 5. This allows
having E/D on either pin 1 or pin 2.
For Optimum Jitter Performance, Pletronics recommends:
A ground plane under the device with any other signals below the ground plane
Minimize other RF signals near device
No large transient signals (both current and voltage) should be routed under the device
Do not layout near a large magnetic field such as a high frequency switching power supply
Do not place near piezoelectric buzzers or mechancial fans
250
200
150
100
50 Seconds
215
°C ± 10°C
10 Seconds max
260
°C max
120 to 160 Seconds
175
°C ± 10°C
T Rise= 4 Degree/second max
Temperature
°C
Reflow Cycle for lead free processing
PECL,
LVDS,
OCXO
Page
1
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7
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