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參數(shù)資料
| 型號： | PE7820DW-FREQ-T250 |
| 廠商： | PLETRONICS INC |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 80 MHz - 250 MHz, PECL OUTPUT |
| 封裝： | PLASTIC, J LEADED PACKAGE-6 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 200K |
| 代理商： | PE7820DW-FREQ-T250 |
LV76D / LV78D Series 2.5 V
LVDS Clock Oscillators
January 2008
www.pletronics.com
425-776-1880
6
6
54
3
2
1
Mechanical:
Inches
mm
B
0.356 +
_0.005
9.04 +
_0.13
C
0.126 +
_0.005
3.21 +
_0.13
D
0.324 +
_0.005
8.23 +
_0.13
F
1
0.050
1.27
Label:
laser marked lettering
FR4 PCB Base:
Solder masked
All via holes tented on bottom
Copper Clad 670 inch (17 m)
Nickel plated 118 inch (3 m)
Gold plated 0.8 inch (0.02 m)
Typical thicknesses
Pin 3 Ground plane is typical
Not to scale
G
1
0.040
1.02
H
1
0.059
1.50
I
1
0.020
0.51
J
1
0.040
1.02
K
1
0.100
2.54
L
1
0.062
1.57
Pad
Function
Note
76
78
1
2
No connect
There is no internal connection to this pad
2
1
Output
Enable/Disable
When this pad is not connected the oscillator shall operate.
When this pad is <0.30 volts, the output will be inhibited (high impedance state.)
Recommend connecting this pad to V
CC if the oscillator is to be always on.
3
Ground (GND)
4
Output
The outputs must be terminated, 100 ohms between the outputs is the ideal
termination.
5
Output*
6
Supply Voltage
(V
CC)
Recommend connecting appropriate power supply bypass capacitors as close as
possible.
Layout and application information
Recommend connecting Pad 1 and Pad 2 together to permit the design to accept Enable/Disable on both
input pads (see LV76D for E/D on pad 1)
For Optimum Jitter Performance, Pletronics recommends:
a ground plane under the device
no large transient signals (both current and voltage) should be routed under the device
do not layout near a large magnetic field such as a high frequency switching power supply
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