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參數(shù)資料
| 型號(hào)： | PEB20321 |
| 廠商： | SIEMENS A G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Multichannel Network Interface Controller for HDLC MUNICH32X |
| 中文描述： | 1 CHANNEL(S), 8.192M bps, SERIAL COMM CONTROLLER, PQFP176 |
| 文件頁(yè)數(shù)： | 161/366頁(yè) |
| 文件大?。?/td> | 4832K |
| 代理商： | PEB20321 |
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PEB 20321
PEF 20321
Local Bus Interface (LBI)
Data Sheet
161
2001-02-14
Bus Arbitration Master Initialization
After reset, the master is normally starting execution out of external memory. During
reset, the default is the arbitration slave mode. The master arbitration mode must first be
selected done by setting the LCONF.ABM =
‘
1
’
. During the initialization, the HDEN bit in
register LCONF must be set. Since the LHOLD pin is held high through the external pull-
up, no hold requests can occur, even when the slave has not been initialized yet.
Note that the HDEN bit of the master can be reset during normal operation to force the
master to ignore hold requests from the slave until HDEN is set again. However, the pins
LHOLD, LHLDA and LBREQ are still reserved for the bus arbitration. This is intended to
have the option to disable certain critical processes against interruption through hold
requests.
Bus Arbitration Slave Initialization
The slave must start using internal resources only after reset. During reset, the default
mode is the slave mode. This is also done by programming the LCONF.ABM =
‘
0
’
. This
enables the slave mode of the bus arbitration signals. After this, the HDEN bit in register
LCONF must be set.
Note: 1. After setting the slave
’
s HDEN bit, the LBREQ output of the slave might be
activated to low for a period of 2TCL. If the master does not recognize this hold
request (it depends on the master
’
s transition detection time slot, whether this
short pulse is detected), this pulse has no effect. If the master recognizes this
pulse, it might go into hold mode for one cycle.
2. It is recommended to not reset the slave
’
s HDEN bit after initialization.
6.2.7.3
The figure
below shows the sequence of the bus arbitration signals in a master/slave
system. The start-up condition is that the master is in normal mode and operating on the
external bus, while the slave is in hold mode, operating from internal memory; the slave
’
s
bus interface is tristated. The marked time points in the diagram are explained in detail
in the following.
1)
The slave detects that it has to perform an external bus access. It activates LBREQ
to low, which issues a hold request to the master.
2)
The master activates LHLDA after releasing the bus. This initiates the slave
’
s exit from
hold sequence.
3a)
When the master detects that it also has to perform external bus accesses, it
activates LBREQ to low. The earliest time for the master to activate LBREQ is one TCL
after the activation of the master
’
s LHLDA signal. However, the slave will ignore this
signal until it has completely taken over control of the external bus. In this way, it is
assured that the slave will at least perform one complete external bus access.
Operation of the Master/Slave Bus Arbitration
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PEF20324 | ICs for Communications |
| PEB20324 | ICs for Communications |
| PEF20532 | 2 Channel Serial Optimized Communication Controller |
| PEB20532 | 2 Channel Serial Optimized Communication Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEB20321-HV2.1 | 制造商:Siemens 功能描述:IC,PROTOCOL CONTROLLER,CMOS,QFP,160PIN |
| PEB20321HV2.2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PEB20321HV22 | 制造商:Infineon Technologies AG 功能描述: |
| PEB20321H-V22 | 功能描述:IC CONTROLR 32-CH HDLC 160-MQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| PEB20324 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:ICs for Communications |
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