參數(shù)資料
型號: PEB2445-N
廠商: SIEMENS A G
元件分類: 路由/交換
英文描述: Multipoint Switching and Conferencing Unit - Attenuation MUSAC-A
中文描述: TELECOM, CONFERENCING CIRCUIT, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 15/70頁
文件大?。?/td> 1236K
代理商: PEB2445-N
PEB 2445
Overview
Semiconductor Group
15
02.96
22
CS
I
Chip Select:
A low level selects the MUSAC-A for
a register access operation.
Supply Voltage:
5 V
±
5 %
Read:
This signal indicates a read operation and is
internally sampled only if CS is active. The
MUSAC-A puts data from the selected internal reg-
ister on the data bus with the falling edge of RD.
RD is active low (Siemens/Intel bus mode).
Write:
This signal initiates a write operation. The
WR input is internally sampled only if CS is active.
In this case the MUSAC-A loads an internal regis-
ter with data from the data bus at the rising edge of
WR. WR is active low (Siemens/Intel bus mode).
Address Latch Enable:
In the Intel type multi-
plexed
μ
P-interface mode a logical high on this line indi-
cates an address of a MUSAC-A internal register
on the external address/data bus. In the Intel type
demultiplexed.
μ
P-interface mode this line is hardwired to
V
SS
, in
the demultiplexed Motorola type
μ
P-interface
mode it should be connected to
V
DD
.
If ALE is not connected it will be set to ground inter-
nally.
Address Data Bus:
If the multiplexed
address/data
μ
P-interface bus mode is selected
these pins transfer data and addresses between
the
μ
P and the MUSAC-A.
23
24
V
DD
RD
I
I
25
WR
I
2
ALE
I
26
27
29
30
31
32
33
34
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
If a demultiplexed mode is used, these bits inter-
face with the system data bus.
1.3
Pin Definitions and Functions
(cont’d)
Pin No.
P-LCC
Symbol
Input (I)
Output (O)
Function
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