參數(shù)資料
型號(hào)： PEB2447H
廠商： SIEMENS AG
英文描述： Memory Time Switch Extended Large MTSXL
中文描述： 內(nèi)存定時(shí)開關(guān)擴(kuò)展大型MTSXL
文件頁(yè)數(shù)： 36/51頁(yè)
文件大?。?/td> 1052K
代理商： PEB2447H
PEB 2447
Detailed Register Description
Semiconductor Group
36
03.97
4.5
Access in demultiplexed
μ
P-interface mode:
Read, address:
Reset value:
Interrupt Status Register (ISTA)
02
H
00
H
FEC
Frame Evaluation Completed
; the indirect register FER contains a
valid offset and can be read.
Procedure Completed
; the procedure started from the command
register (CM reset or MTSXL selftest) is finished.
Initialization Request
. The connection memory has to be
programmed due to a loss of data (IR = 1). The IR bit is set after
power failure or inappropriate clocking. It can only be retriggered
again after a selftest or CM reset procedure.
PCM Framing Interrupt
; this bit being logical 1 indicates the loss or
gain of synchronization. Synchronization is considered lost by the
MTSXL if the SP signal is not repeated within the correct period.
Synchronization is considered achieved, if two consecutive SP
pulses with the correct period have been received.
Any interrupt will activate the INT line if it is not masked. All interrupt bits and the INT line
are reset when reading ISTA.
Note 1: All interrupts and the INT line are cleared with reset.
PC
IR
PFI
Note 2: If the SP signal is repeated within a multiple of frame length
(e.g. 2
×
or 4
×
125
μ
s) but at correct phase:
– the MTSXL works correctly because the internal counters run autonomously
and are synchronized within correct phase.
– the PFI interrupt does not occur because this situation is internally handled as
“l(fā)oss of synchronization” and this situation does not change.
Note 3: During selftest no PFI interrupt will occur.
Bit 7
Bit 0
0
0
0
0
FEC
PC
IR
PFI
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參數(shù)描述
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