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參數(shù)資料
| 型號： | PEB2466-H |
| 英文描述： | LTC3409 Evaluation Kit |
| 中文描述： | A-Law/u-Law編解碼器 |
| 文件頁數(shù)： | 54/73頁 |
| 文件大?。?/td> | 1618K |
| 代理商： | PEB2466-H |
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PEB 2466
PEF 2466
Application Hints
Hardware Reference Manual
45
2001-02-20
7.3
Proposal for SICOFI
4-μC Board Design
For a new layout design it is recommended to use a separate ground-layer which gives
the possibilty to connect all ground-pins of the SICOFI
4-μC (GNDA and GNDD) low-
ohmic together.
Furthermore, an optimum board layout should follow these recommendations
Separate all digital supply lines from analog supply lines as far as possible
Applying the standard practice regarding blocking capacitors is recommended
Place all SLIC circuits as close as possible to the Vinx/Voutx pins of the SICOFI
Separate all analog circuitry (especially SLIC and Vinx/Voutx) as far as possible from
any digital signal source (esp. clock signals)
Figure 28
Proposal for a ground concept
VDD is the grey colored layer and the Ground-plane is the black colored layer. The
Ground-plane should be on both sides of the board on the top and on the ground layer.
49
51
53
52
55 56
58
57
60
62
61
64
100 nF
Ceramic
GND
Connector
1-10
Tantal
next to the
connector pins
F
V
DD
Connector
μ
PEB 2466 H
Ground-
plane
D
G
V
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
24
22
23
25
26
27
28
29
30
31
32
G
54
G
59
G
63
V
D
G
50
V
D
V
R
21
D
V
Ceramic
nF
Ceramic
nF
100
nF
100
nF
220
Ceramic
100
The ground-plane should
be used for shielding
SICOFI4-μC V2.2
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| PEB2466HV2.2 | 功能描述:接口—CODEC POTS RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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