參數(shù)資料
型號: PEB2466
廠商: SIEMENS AG
元件分類: Codec
英文描述: Four Channel Codec Filter with PCM- and m-Controller Interface SICOFI4-mC
中文描述: 四信道編解碼器與PCM -和m -控制器接口SICOFI4,胞嘧啶
文件頁數(shù): 51/82頁
文件大?。?/td> 3330K
代理商: PEB2466
PEB 2466
Programming the SICOFI
-4-
μ
C
Semiconductor Group
51
02.97
RESET (Basic Setting Mode)
Upon initial application of
V
DD
or resetting pin RESET to ‘0’ during operation, or by
software-reset (see XOP command), the SICOFI-4-
μ
C enters a basic setting mode.
Basic setting means, that the SICOFI-4-
μ
C configuration registers CR0... CR6 and
XR0... XR7 are initialized to ‘0’ for all channels.
All programmable filters are disabled, all programmable command/indication pins are
inputs. The two tone generators as well as any testmodes are disabled. There is no
persistence checking. Receive signaling registers are cleared. DOUT-pin is in high
impedance state, the analog outputs and the signaling outputs are forced to ground.
If any voltage is applied to any input-pin before initial application of
V
DD
, the SICOFI-4-
μ
C
may not enter the basic setting mode. In this case it is necessary to reset the
SICOFI-4-
μ
C or to initialize the SICOFI-4-
μ
C configuration registers to ‘0’.
The SICOFI-4-
μ
C leaves this mode automatically after the RESET-pin is released.
Standby Mode
After releasing the RESET-pin, (RESET-state), the SICOFI-4-
μ
C will enter the Standby
mode. The SICOFI-4-
μ
C is forced to standby mode with the PU-bit set to ‘0’ in the
CR1-register (POWERDOWN). All 4 channels must be programmed separately. During
standby mode the serial SICOFI-4-
μ
C
μ
-Controller interface is ready to receive and
transmit commands and data. Received voice data on DRA, DRB-pin will be ignored.
SICOFI-4-
μ
C configuration registers and Coefficient-RAM can be loaded and read back
in this mode. Data on signaling input pins can be read via the
μ
-Controller interface.
CR0.. CR6
XR0.. XR7
Coefficient-RAM
Command Stack
DIN-input
DOUT-output
VOUT1,2,3,4
SBx_y
SOx_y
00
H
00
H
Old value
Cleared
Ignored
High impedance
GNDA1,2,3,4
Input
GNDD
DXA, DXB
VOUT1, 2, 3, 4
High ‘Z’
GNDA1, 2, 3, 4
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