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參數(shù)資料
| 型號： | PEB3445E |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 54/211頁 |
| 文件大小： | 2567K |
| 代理商： | PEB3445E |
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PEB 3445 E
Functional Description
Data Sheet
54
2001-06-29
Data Transmission
Transmission of BOM data is done by using a transparent mode of the signalling
controller. After having written 1 to 32 bytes to the transmit FIFO, the command ’Start
Transmission, Enable Automatic Repetition’ via the handshake register FHND forces the
TE3-MUX to repeatedly transmit the data stored in the transmit FIFO to the remote end.
The cyclic transmission continues until a reset command (FHND.XRES) is issued or until
the command ‘Stop Transmission, Disable Automatic Repetition’ is written to the
handshake register FHND. Afterwards an all ‘1’ pattern is transmitted.
The transmitter does not insert FF
H
itself. Data stored in the transmit FIFO has to include
the FF
H
byte as well and has to follow the following byte format:
111111110xxxxxx0
B
Data Reception BOM Regular Mode
The following byte format is assumed (the left most bit is received first):
111111110xxxxxx0
B
The signalling controller uses the first two FF
H
bytes for synchronization, the next byte
is stored in the receive FIFO (first bit received: LSB) if it starts and ends with a ‘0’, that
is the receiver automatically removes the FF
H
synchronization byte. Bytes starting or
ending with a ‘1’ are not stored. If the message word 7E
H
(similar to HDLC flag) is
received or when more than four times FF
H
is received byte sampling is stopped and a
’Receive Message End’ interrupt vector is generated. Byte sampling starts again when
the synchronization byte FF
H
is received two times.
After detecting 32 bits of ‘1’s, byte sampling is stopped, the receive status byte marking
the end of a BOM frame is stored in the receive FIFO and a ’BOM Idle’ interrupt is
generated. The same interrupt is generated when not eight consecutive ones where
received in 32 bits.
Data Reception BOM Filter Mode
In BOM filter mode the received BOM data is validated and then filtered. If same valid
BOM pattern is received for 7 out of 10 patterns, then BOM data is written to the receive
FIFO along with the status byte indicating that filtered BOM data was received.
Filtered BOM mode will be exited if one of the following conditions occurs:
4 valid BOM patterns are consecutively received but none of these equals the BOM
data received earlier.
4 times idle pattern is received.
4.6.3
Access to the FIFO’s of the signalling controllers is handled via registers. The
corresponding FIFO’s for receive and transmit direction of the C-bit parity Path
Signalling controller FIFO operation
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