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參數(shù)資料
| 型號(hào)： | PEEL16CV8S-25 |
| 英文描述： | CMOS Programmable Electrically Erasable Logic Device |
| 中文描述： | 的CMOS電可擦除可編程邏輯器件 |
| 文件頁(yè)數(shù)： | 2/11頁(yè) |
| 文件大?。?/td> | 386K |
| 代理商： | PEEL16CV8S-25 |
Anachip Corp.
www.anachip.com.tw Rev. 1.0 Dec 16, 2004
2/11
Functional Description
The PEEL
TM
16CV8 implements logic
functions as sum-of- products
expressions in
a programmable-AND/fixed-OR logic array. User-defined
functions are created by programming the connections of input signals
into the
array. User-configurable
output structures in the
form of
macro-
cells further increase logic flexibility.
Architecture Overview
The PEEL
TM
16CV8
features ten
dedicated input pins and
eight I/O pins,
which allow a total of up to 16 inputs and 8 outputs for creating
logic
functions. At the core of the
device
is
a programmable electrically-eras-
able AND
array which drives a
fixed OR
array.
With this structure the
PEEL
TM
16CV8 can implement
up to 8 sum-of-products logic expres-
sions.
Associated with each of
the
eight OR functions
is a macrocell which
can
be independently programmed to one of up to four different basic config-
urations.
The
programmable
macrocells
allow
each
I/O
to
create
sequential or combinatorial logic functions
of active-high or active-low
polarity, while providing two possible feedback paths into the array.
Three different device modes, Simple, Complex, and
Registered, sup-
port various user configurations. In
Simple mode
a macrocell can be
configured for combinatorial function
with the output buffer permanently
enabled, or the output
buffer can
be disabled and the
I/O
pin used as a
dedicated input. In Complex mode a macrocell
is configured for combi-
natorial
function with
the output buffer enable
controlled
by a
product
term.
In Registered
mode, a macrocell can be
configured for registered
operation
with
the register
clock and
output buffer enable controlled
directly from pins, or can be
configured for combinatorial function
with the
output buffer enable controlled by a
product
term.
In most cases the
device
mode
is set automatically by the
development software,
based on
the features specified in the design.
64 product terms:
-56
product terms (arranged in
8 groups of 7) form sum-of-product
functions for macrocell combinatorial or registered logic
-8 product terms (arranged 1
per
macrocell) add an
additional
product
term for macrocell sum-of-products functions or I/O pin
output enable control
At
each input-line/product-term
intersection there is an EEPROM mem-
ory cell
which determines
whether or
not there is a
logical connection at
that intersection.
Each
product term is
essentially a 32-input AND gate. A
product term which is
connected to
both
the true and
complement of an
input signal will
always be
FALSE
and thus will not
affect the
OR
function that
it drives. When all
the connections
on a product term are
opened, that term will always be TRUE.
When programming the PEEL
TM
16CV8,
the device programmer first
performs a
bulk erase
to remove the
previous pattern. The
erase
cycle
opens every logical connection in the array. The device is configured to
perform the user-defined function by programming selected
connections
in the AND array. (Note that PEEL
TM
device programmers automatically
program all of the connections on unused product terms so that they will
have no effect on the output function.
The
three
device
modes
support
designs
created
explicitly
for
the
PEEL
TM
16CV8,
as well as designs created originally for popular PLD
devices such as the
16R4, 16R8, and 16L8. Table 1 shows the
device
mode
used to emulate the various PLDs. Design conversion into the
16CV8
is
accommodated
by
JEDEC-to-JEDEC
translators
available
from Anachip, as
well as
several
programmers which
can read
the origi-
nal PLD JEDEC file and
automatically program the
16CV8 to perform the
same function.
AND/OR Logic Array
The programmable
AND
array of the
PEEL
TM
16CV8 is
formed by input
lines intersecting
product terms. The input lines
and
product terms are
used as follows:
32 input lines:
-16 input
lines
carry the true
and
complement of
the signals applied
to the 8 dedicated input pins
-16 additional lines carry
the true
and complement
of 8 macrocell
feedback signals or inputs from I/O pins or the clock/ OE pins
Table 1 : PEEL
TM
16CV8 Device Compatibility
PLD Architecture
Compatibility
10H8
10L8
10P8
12H6
12L6
12P6
14H4
14L4
14P4
16H2
16HD8
16L2
16LD8
16P2
16H8
16L8
16P8
16R4
16R6
16R8
16RP4
PEEL
TM
16CV8
Device Mode
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Complex
Complex
Complex
Registered
Registered
Registered
Registered
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PEEL16CV8S-25L | CMOS Programmable Electrically Erasable Logic Device |
| PEEL16CV8J-25 | CMOS Programmable Electrically Erasable Logic Device |
| PEEL16CV8J-25L | CMOS Programmable Electrically Erasable Logic Device |
| PEEL16CV8 | CMOS Programmable Electrically Erasable Logic Device |
| PEEL16CV8P-25 | CMOS Programmable Electrically Erasable Logic Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEEL16CV8S-25L | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 10 Input 8 I/O 25ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PEEL16CV8SI-25 | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 10 INP 8 I/O 25ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PEEL16CV8SI-25L | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 10 Input 8 I/O 25ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PEEL16CV8T15 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Logic IC |
| PEEL16CV8T25 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Logic IC |
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