參數(shù)資料
型號: PEEL18LV8ZJ-15
英文描述: CMOS Programmable Electrically Erasable Logic Device
中文描述: 的CMOS電可擦除可編程邏輯器件
文件頁數(shù): 8/10頁
文件大小: 230K
代理商: PEEL18LV8ZJ-15
Table 4 - A.C. Electrical Characteristics
Over the operating range
9
Anachip Corp.
www.anachip.com.tw Rev. 1.0 Dec 16, 2004
8/10
-15/I-15
3V
±
10%
Min Max Min Max
20
3.3V
±
10%
Symbol
Parameter
Units
tPD
Input
6
to non-registered output in continuous mode
13
Input
6
to output enable
7
15
ns
tOE
20
15
ns
tOD
Input
6
to output disable
7
20
15
ns
tCO1
Clock to Output
17
12
ns
tCO2
Clock to comb output delay via internal registered
feedback
Clock to Feedback
30
25
ns
tCF
13
8
ns
tSC
Input
6
or feedback setup to clock
17
12
ns
tHC
Input
6
hold after clock
0
0
ns
tCL, tCH
Clock low time, clock high time
9
15
10
ns
tCP
Min clock period Ext (tSC + tCO1 )
32
24
ns
fMAX1
Internal feedback 1/ (tSC + tCF)
12
33.3
50
MHz
fMAX2
External Feedback (1/ tCP)
12
31.25
41.67
MHz
fMAX3
No Feedback 1/ (tCL + tCH)
12
33.3
50
MHz
tAW
Asynchronous Reset Pulse Width
20
15
ns
tAP
Input to Asynchronous Reset
20
15
ns
tAR
Asynchronous Reset recovery time
20
15
ns
tRESET
Power-on reset time for registers in clear state
14
5
5
μ
s
Inputs I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
Figure 7 - Switching Waveforms
Notes:
1.
Minimum DC input is -0.5V, however, inputs may undershoot to
-2.0V for periods less than 20 ns.
V
I
and V
O
are not specified for program / verify operation.
The Supply Voltage range of 2.7 to 3.6V was chosen to allow
this part to be used in both 3V
±
10% and 3.3V
±
10%
applications.
Test Points for Clock and VCC in t
R
and t
F
are referenced at
the 10% and 90% levels.
I/O pins are 0V and V
CC
.
"Input" refers to an input pin signal.
t
OE
is measured from input transition to V
REF
±
0.1V, T
OD
is
measured from input transition to V
OH
-0.1V or V
OL
+0.1V;
V
REF
=V
L.
2.
3.
4.
5.
6.
7.
8.
9.
Capacitances are tested on a sample basis.
Test conditions assume: signal transition times of 3ns or less
from the 10% and 90% points, timing reference levels of 1.5V
(Unless otherwise specified).
Test one output at a time for duration of less than 1 second.
I
CC
for a typical application: This parameter is tested with the
device programmed as an 8-bit Counter.
Parameters are not 100% tested. Specifications are based on
initial characterization and are tested after any design process
modification that might affect operational frequency.
t
PD
, t
OE
, t
OD
, t
CO
, t
SC
, and t
AP
are approximately 5 ns.
slower on the first transaction from sleep mode.
All inputs at GND.
10.
11.
12.
13.
14.
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