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參數(shù)資料
| 型號(hào)： | PEEL18LV8ZJI-15 |
| 英文描述： | CMOS Programmable Electrically Erasable Logic Device |
| 中文描述： | 的CMOS電可擦除可編程邏輯器件 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 230K |
| 代理商： | PEEL18LV8ZJI-15 |
the asynchronous clear sets Q LOW, regardless of the
clock state. If both terms are satisfied simultaneously, the
clear will override the preset.
Anachip Corp.
www.anachip.com.tw Rev. 1.0 Dec 16, 2004
4/10
Output Polarity
Each macrocell can be configured to implement active-high
or active-low logic. Programmable polarity eliminates the
need for external inverters.
Output Enable
The output of each I/O macrocell can be enabled or
disabled under the control of its associated programmable
output enable product term. When the logical conditions
programmed on the output enable term are satisfied, the
output signal is propagated to the I/O pin. Otherwise, the
output buffer is switched into the high-impedance state.
Under the control of the output enable term, the I/O pin can
function as a dedicated input, a dedicated output, or a bi-
directional I/O. Opening every connection on the output
enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically false and the
I/O will function as a dedicated input.
Input/Feedback Select
The PEEL18LV8Z macrocell also provides control over the
feedback path. The input/feedback signal associated with
each I/O macrocell can be obtained from three different
locations; from the I/O input pin, from the Q output of the
flip-flop (registered feedback), or directly from the OR gate
(combinatorial feedback).
Bi-directional I/O
The input/feedback signal is taken from the I/O pin when
using the pin as a dedicated input or as a bi-directional I/O.
(Note that it is possible to create a registered output
function with a bi-directional I/O, refer to Figure 4).
Figure 4 - PEEL18LV8Z I/O Macro cell
Combinatorial Feedback
The signal-select multiplexer gives the macrocell the ability
to feedback the output of the OR gate, bypassing the
output buffer, regardless of whether the output function is
registered or combinatorial. This feature allows the creation
of asynchronous latches, even when the output must be
disabled. (Refer to configurations 5, 6, 7, and 8 in Figure 5.)
Registered Feedback
Feedback also can be taken from the register, regardless
of whether the output function is programmed to be
combinatorial or registered. When implementing a
combinatorial output function, registered feedback allows
for the internal latching of states without giving up the use
of the external output.
Programmable Clock Options
A unique feature of the PEEL18LV8Z is a programmable
clock multiplexer that allows the user to select true or
complement forms of either input pin or product-term clock
sources.
Operates in both 3 Volt and 3.3 Volt Systems
The PEEL18LV8Z is designed to operate with a V
CC
range
of 2.7 to 3.6 Volts D.C. This allows operation in both 3 Volt
10% (battery operated) and 3.3 Volt 10% (power supply
operated) systems. The propagation delay t
PD
is 5 ns
slower at the lower voltage, but this is typically not an issue
in battery-operated systems (see - A.C. Electrical
CharacteristicsTable 1 - Absolute Maximum Ratings- A.C.
Electrical Characteristics).
Schmitt Trigger Inputs
The PEEL18LV8Z has Schmitt trigger input buffers on all
inputs, including the clock. Schmitt trigger inputs allow
direct input of slow signals such as biomedical and sine
waves or clocks. They are also useful in cleaning up noisy
signals. This makes the PEEL18LV8Z especially desirable
in portable applications where the environment is less
predictable.
Zero Power Feature
The CMOS PEEL18LV8Z features "Zero-Power" standby
operation for ultra-low power consumption. With the "Zero-
Power" feature, transition-detection circuitry monitors the
inputs, I/Os (including CLK) and feedbacks. If these signals
do not change for a period of time greater than
approximately three t
PD
's, the outputs are latched in their
current state and the device automatically powers down.
When the next signal transition is detected, the device will
"wake up" for active operation until the signals stop
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| PEEL18LV8ZJI-15L | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 10 INP 8 I/O 15ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PEEL18LV8ZJI-25 | 制造商:ANACHIP 制造商全稱(chēng):Anachip Corp 功能描述:CMOS Programmable Electrically Erasable Logic Device |
| PEEL18LV8ZJI-25L | 制造商:ANACHIP 制造商全稱(chēng):Anachip Corp 功能描述:CMOS Programmable Electrically Erasable Logic Device |
| PEEL18LV8ZJI-35 | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 10 INP 8 I/O 35ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PEEL18LV8ZJI-35L | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 10 INP 8 I/O 35ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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