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參數(shù)資料
| 型號： | PEF20571 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | DSP Embedded Line and Port Interface Controller |
| 中文描述： | DSP嵌入式線和港口接口控制器 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 170K |
| 代理商： | PEF20571 |
PEB 20570/PEF 20570
PEB 20571/PEF 20571
Addendum to “DELIC Clock System Synchronization”
Addendum
3/8
2003-08-04
The time within the DELIC DCXO guarantees the 100 ppm clock accuracy varies,
depending on various conditions. When the central office deactivates, the user will be
notified by the DELIC. It is up to the user to provide another clock source (for example
REFCLK) for the DCXO as soon as possible.
1.2
VIP clocked
in LT-T Mode
by an external Crystal
Figure 2
Clocking the VIP by using external Crystal
As shown in
Figure 2
no unstable system can occur by using an external crystal rather
than the DELIC Layer 1 clock as VIP clock source in LT-T mode. When the central office
line is deactivated, the VIP takes the 15.36 MHz oscillator signal and divides it by 10.
This signal is used as XCLK input of the DELIC DCXO. Since the VIP 15.36 MHz signal
is entirely independent from the DELIC clocking system no unstable system can occur.
Note: In LT-T mode it is recommended to use an external crystal to clock the VIP.
DELIC_refclk2
VIP
Central
Office
OSC
RxPLL
DCXO
/10
Mux
15.36 MHz
16.384 MHz
Divider
PD
PLL
Divider
1.536 MHz
Divider
8kHz
XCLK
REFCLK
16.384 MHz
DELIC
MUX
REFCLK
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