參數(shù)資料
型號(hào)： PEF81902F
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Power Factor Controller; Package: SO; No of Pins: 16; Temperature Range: 0°C to +70°C
中文描述： ？4B3T第二代模塊化綜合業(yè)務(wù)數(shù)字網(wǎng)新臺(tái)幣（智能擴(kuò)展）？
文件頁(yè)數(shù)： 53/276頁(yè)
文件大?。?/td> 3611K
代理商： PEF81902F
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PEF 81912/81913
Functional Description
Data Sheet
37
2001-03-30
Monitoring TIC Bus
Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be
monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring)
bit in the control registers CRx. The TSDPx0 must be set to 08
h
for monitoring from DU
or 88
h
for monitoring from DD. By this it is possible to monitor the TIC bus (TS11) and
the odd numbered D-channel (TS3) simultaneously on DU and DD.
Synchronous Transfer
While looping, shifting and switching the data can be accessed by the controller between
the synchronous transfer interrupt (STI) and the synchronous transfer overflow interrupt
(STOV).
The microcontroller access to each of the CDAxy registers can be synchronized by
means of four programmable synchronous transfer interrupts (STIxy)
1)
and synchronous
transfer overflow interrupts (STOVxy)
2)
in the STI register.
Depending on the DPS bit in the corresponding TSDPxy register the STIxy is generated
two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected time slot
(CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks.
In the following description the index xy
0
and xy
1
are used to refer to two different
interrupt pairs (STI/STOV) out of the four CDA interrupt pairs (STI10/STOV10, STI11/
STOV11, STI20/STOV20, STI21/STOV21).
A STOVxy
0
is related to its STIxy
0
and is only generated if STIxy
0
is enabled and not
acknowledged. However, if STIxy
0
is masked, the STOVxy0 is generated for any other
STIxy1 which is enabled and not acknowledged.
Table 10
gives some examples for that. It is assumed that a STOV interrupt is only
generated because a STI interrupt was not acknowledged before.
In example 1 only the STIxy
0
is enabled and thus STIxy
0
is only generated. If no STI is
enabled, no interrupt will be generated even if STOV is enabled (example 2).
In example 3 STIxy
0
is enabled and generated and the corresponding STOVxy
0
is
disabled. STIxy
1
is disabled but its STOVxy
1
is enabled, and therefore STOVxy
1
is
generated due to STIxy
0
. In example 4 additionally the corresponding STOVxy
0
is
enabled, so STOVxy
0
and STOVxy
1
are both generated due to STIxy
0
.
In example 5 additionally the STIxy
1
is enabled with the result that STOVxy
0
is only
generated due to STIxy
0
and STOVxy
1
is only generated due to STIxy
1
.
Compared to the previous example STOVxy
0
is disabled in example 6, so STOVxy
0
is
not generated and STOVxy
1
is only generated for STIxy
1
but not for STIxy
0
.
1)
In order to enable the STI interrupts the input of the corresponding CDA register has to be enabled. This is also
valid if only a synchronous write access is wanted. The enabling of the output alone does not effect an STI
interrupt.
2)
In order to enable the STOV interrupts the output of the corresponding CDA register has to be enabled. This
is also valid if only a synchronous read access is wanted. The enabling of the input alone does not effect an
interrupt.
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