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參數(shù)資料
| 型號： | Pentium OverDrive Processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術(shù)奔騰超速轉(zhuǎn)動處理器) |
| 中文描述： | 奔騰過驅(qū)動處理器的MMX技術(shù)的Pentium處理器為基礎(chǔ)的系統(tǒng)（帶MMX公司技術(shù)奔騰超速轉(zhuǎn)動處理器） |
| 文件頁數(shù)： | 14/61頁 |
| 文件大?。?/td> | 481K |
| 代理商： | PENTIUM OVERDRIVE PROCESSOR |
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Pentium
OverDrive
PROCESSOR WITH MMX
TECHNOLOGY
E
14
9/8/97 11:55 AM 29060701.DOC
PRELIMINARY
2.3.
Quick Pin Reference
Table 2. Quick Pin Reference
Symbol
Type
Name and Function
A20M#
I
When the
address bit 20 mask
pin is asserted, Pentium
OverDrive
processor
with MMX technology emulates the address wraparound at 1 Mbyte which
occurs on the 8086. When A20M# is asserted, the Pentium OverDrive
processor with MMX technology masks physical address bit 20 (A20) before
performing a lookup to the internal caches or driving a memory cycle on the bus.
The effect of A20M# is undefined in protected mode. A20M# must be asserted
only when the processor is in real mode.
A31-A3
I/O
As outputs, the address lines of the processor along with the byte enables
define the physical area of memory or I/O accessed. The external system drives
the inquire address to the processor on A31-A3.
ADS#
O
The address status indicates that a new valid bus cycle is currently being driven
by the Pentium OverDrive processor with MMX technology.
ADSC#
O
ADSC# is functionally identical to ADS#.
AHOLD
I
In response to the assertion of address hold, Pentium OverDrive processor with
MMX technology will stop driving the address lines (A31-A3), and AP in the next
clock. The rest of the bus will remain active so data can be returned or driven for
previously issued bus cycles.
AP
I/O
Address parity is driven by the Pentium OverDrive processor with MMX
technology with even parity information on all the Pentium OverDrive processor
with MMX technology generated cycles in the same clock that the address is
driven. Even parity must be driven back to the Pentium OverDrive processor
with MMX technology during inquire cycles on this pin in the same clock as
EADS# to ensure that correct parity check status is indicated by the Pentium
OverDrive processor with MMX technology
APCHK#
O
The
address parity check
status pin is asserted two clocks after EADS# is
sampled active if the Pentium OverDrive processor with MMX technology has
detected a parity error on the address bus during inquire cycles. APCHK# will
remain active for one clock each time a parity error is detected (including during
dual processing private snooping).
[APICEN]
PICD1
I
The APIC is not supported by the Pentium OverDrive processor with MMX
technology.
BE7#-BE5#
BE4#-BE0#
O
I/O
The
byte enable
pins are used to determine which bytes must be written to
external memory, or which bytes were requested by the CPU for the current
cycle. The byte enables are driven in the same clock as the address lines
(A31-3).
[BF]
[BF1]
I
Bus Frequency
determines the bus-to-core frequency ratio on the Pentium
processor. These are Internal No Connects on the Pentium OverDrive
processor with MMX technology which has a preset bus fraction of 5/2 for 166-
MHz OverDrive Processor and 3/1 for 200-MHz OverDrive Processor core/bus
ratio.
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