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參數(shù)資料
| 型號(hào)： | PEX8624-AARDK |
| 廠商： | PLX Technology, Inc. |
| 英文描述： | PCIe Gen2, 5.0GT/s 24-lane, 6-port Switch |
| 中文描述： | 的PCIe Gen2，5.0GT / s的24路，6端口交換機(jī) |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 225K |
| 代理商： | PEX8624-AARDK |
Preliminary - PLX Confidential
Dual-Host & Failover Support
The PEX 8624 product supports a
Non-Transparent
(NT) Port,
which enables the implementation of
multi-
host systems
in communications, storage, and blade
server applications.
The NT port
allows systems to
isolate host
memory domains
by presenting the
processor
subsystem as an
endpoint rather
than another
memory system.
Base address
registers are used
to translate addresses; doorbell registers are used to send
interrupts between the address domains; and scratchpad
registers (accessible by both CPUs) allow inter-
processor communication (see Figure 2).
Dual Cast
The PEX 8624 supports Dual Cast, a feature which
allows for the copying of data (e.g. packets) from one
ingress port to two egress ports allowing for higher
performance in dual-graphics, storage, security, and
redundant applications.
Read Pacing
The Read Pacing feature allows users to throttle the
amount of read requests being made by downstream
devices. When a downstream device requests several
long reads back-to-back, the Root Complex gets tied up
in serving this downstream port. If this port has a narrow
link and is therefore slow in receiving these read packets
from the Root Complex, then other downstream ports
may become starved – thus, impacting performance. The
Read Pacing feature enhances performances by allowing
for the adequate servicing of all downstream devices.
Hot Plug for High Availability
Hot plug capability allows users to replace hardware
modules and perform maintenance without powering
down the system. The PEX 8624 hot plug capability
feature makes it suitable for
High Availability (HA)
applications
. Three downstream ports include a
Standard Hot Plug Controller. If the PEX 8624 is used in
an application where one or more of its downstream
ports connect to PCI Express slots, each port’s Hot Plug
Controller can be used to manage the hot-plug event of
its associated slot. Every port on the PEX 8624 is
equipped with a hot-plug control/status register to
support hot-plug capability through external logic via the
I
2
C interface.
SerDes Power and Signal Management
The PEX 8624 supports software control of the SerDes
outputs to allow optimization of power and signal
strength in a system. The PLX SerDes implementation
supports four levels of power – off, low, typical, and
high. The SerDes block also supports
loop-back modes
and
advanced reporting of error conditions
, which
enables efficient management of the entire system.
Interoperability
The PEX 8624 is designed to be fully compliant with the
PCI Express Base Specification r2.0, and is backwards
compatible to PCI Express Base Specification r1.1 and
r1.0a. Additionally, it supports
auto-negotiation
,
lane
reversal
, and
polarity reversal
. Furthermore, the PEX
8624 is designed for Microsoft Vista compliance. All
PLX switches undergo thorough interoperability testing
in PLX’s
Interoperability Lab
and
compliance testing
at the PCI-SIG plug-fest.
Applications & Usage Models
Suitable for
host-centric
as well as
peer-to-peer traffic
patterns,
the PEX 8624 can be configured for a broad
range of form factors and applications.
Host Centric Fan-out
The PEX 8624, with its symmetric or asymmetric lane
configuration capability, allows user-specific tuning to a
variety of host-centric applications. Figure 3 shows a
typical
workstation
design where the root complex
provides a PCI Express link that needs to be expanded to
a larger number of smaller ports for a variety of I/O
functions. In this example, the PEX 8624 has an 8-lane
upstream port, and four downstream ports using x4 links.
The PEX 8624 can also be used to create PCIe Gen1 (2.5
Gbps) ports. The PEX 8624 is backwards compatible
with PCIe Gen1 devices. Therefore, the PEX 8624
enables a Gen 2 native Chip Set to fan-out to Gen 1
endpoints. In Figure 3, the PCIe slots connected to the
PEX 8624’s downstream ports can be populated with
either PCIe Gen1 or PCIe Gen 2 devices. Conversely,
the PEX 8624 can also be used to create Gen 2 ports on
a Gen 1 native Chip Set in the same fashion.
I/O
Figure 2. Non-Transparent Port
I/O
I/O
Blade
CPU
Host
Primary
Non-Transparent
Port
PEX 8624
NT
Blade
CPU
Host
Secondary
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEX8624-AB-RDK | 功能描述:界面開發(fā)工具 PEX 8624 Rapid Development Kit RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PEX8624-BA RDK | 功能描述:界面開發(fā)工具 DEVELOPMENT KIT RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PEX8624-BB RDK | 制造商:PLX Technology 功能描述: |
| PEX8624-BB50BIF | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 24 Lane, 6 Port PCI Express Gen 2 Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PEX8624-BB50RBC F | 功能描述:PCI Express? Switch IC 324-FCBGA (19x19) 制造商:broadcom limited 系列:ExpressLane? 包裝:托盤 零件狀態(tài):在售 應(yīng)用:PCI Express? 多路復(fù)用器/解復(fù)用器電路:- 開關(guān)電路:- 通道數(shù):- 導(dǎo)通電阻（最大值）:- 電壓 -?電源，單（V+）:- 電壓 - 電源，雙（V±）:- -3db 帶寬:- 特性:可配置 工作溫度:- 封裝/外殼:- 供應(yīng)商器件封裝:324-FCBGA（19x19） 標(biāo)準(zhǔn)包裝:420 |
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