參數(shù)資料
型號(hào): PGA2500IDBR
英文描述: Digitally Controlled Microphone Preamplifier
中文描述: 數(shù)控麥克風(fēng)前置放大器
文件頁(yè)數(shù): 7/16頁(yè)
文件大?。?/td> 197K
代理商: PGA2500IDBR
"#$%%
SBOS289A NOVEMBER 2003 REVISED DECEMBER 2003
www.ti.com
7
OVERVIEW
The PGA2500 is a digitally controlled microphone
preamplifier integrated circuit designed for amplifying the
output of dynamic and condenser microphones and
driving
high
performance
converters (ADCs). A functional block diagram of the
PGA2500 is shown in Figure 1.
The analog input to the preamplifier is provided
differentially at the V
IN
+ and V
IN
inputs (pins 27 and 26,
respectively). The programmable gain amplifier can be
programmed to either pass through the signal at unity gain,
or apply 10dB to 65dB of gain to the input signal. The gain
of the amplifier is adjustable over the full 10dB to 65dB
range in 1dB steps. The differential output of the PGA2500
is made available at V
OUT
+ and V
OUT
(pins 17 and 16,
respectively). Gain is controlled using a serial port
interface.
audio
analog-to-digital
The four-wire serial port interface is used to program the
PGA2500 gain and support functions. A 16-bit control
word is utilized to program these functions (see Figure 2,
page 9). A serial data output pin provides support for
daisy-chaining multiple PGA2500 devices on a single
serial interface bus (see Figure 4, page 10).
The differential analog output of the PGA2500 is
constantly monitored by a DC servo amplifier loop. The
purpose of the servo loop is to minimize the DC offset
voltage present at the analog outputs by feeding back an
error signal to the input stage of the programmable gain
amplifier. The error signal is then used to correct the offset.
The DC servo may be disabled by driving the DCEN input
(pin 7) high or setting the DC bit in the serial control word
to 1. Normally, the DCEN pin is connected to DGND to
enable the DC servo, while the DC bit is set to 0.
SERIAL
PORT and
LOGIC
CONTROL
C
and C
are external DC servo integrator capacitors,
and are connected across the C
S11
/C
S12
and C
S21
/C
S22
pins, respectively.
CS
SCLK
SDI
SDO
OVR
V
COM
IN
V
OUT
+
V
OUT
VD
DGND
DCEN
0dB
ZCEN
GPO1
GPO2
GPO3
GPO4
PGA
DC
Servo
C
S1
C
S2
V
IN
+
V
IN
AGND
VA+
VA+
VA
VA
Gain Range
0dB or
+10dB to +65dB
1dB per step
Figure 1. PGA2500 Functional Block Diagram
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