5.0Gbps 4-Lane PCIe 2.0 ReDdriver
參數(shù)資料
型號(hào): PI2EQX5864CZFE
廠商: Pericom
文件頁(yè)數(shù): 20/20頁(yè)
文件大?。?/td> 0K
描述: IC PCI-E REDRIVER 56TQFN
標(biāo)準(zhǔn)包裝: 66
系列: ReDriver™
類(lèi)型: 轉(zhuǎn)接驅(qū)動(dòng)器
Tx/Rx類(lèi)型: CML
電容 - 輸入: 50pF
電源電壓: 1.15 V ~ 1.25 V
電流 - 電源: 800mA
安裝類(lèi)型: 表面貼裝
封裝/外殼: 56-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 56-TQFN-EP(5x11)
包裝: 管件
9
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe 2.0 ReDdriver
with Equalization, Emphasis and I2C Control
Acknowledge
Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH) during the acknowledge
clock pulse, the PI2EQX5864C will pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW dur-
ing the HIGH period of this clock pulse as indicated in the I2C Data Transfer diagram. The PI2EQX5864C will generate an acknowl-
edge after each byte has been received.
Data Transfer
A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, the PI2EQX5864C will watch the next
byte of information for a match with its address setting. When a match is found it will respond with a read or write of data on the
following clocks. Each byte must be followed by an acknowledge bit, except for the last byte of a read cycle which ends with a stop
bit. For a write cycle, the rst data byte following the address byte is a dummy or ll byte that is not used by the PI2EQX5864C.
This byte is provided to provided compatibility with systems implementing 10-bit addressing. Data is transferred with the most
signicant bit (MSB) rst. After each block write, address pointer will reset to byte 0.
Byte 1 - Receiver Detect Output Register (RX50)
RX50_xy = 1 = load detected, RX50_xy = 0 = No receiver found
Bit
76543210
Name
RX50_A0
RX50_B0
RX50_A1
RX50_B1
RX50_A2
RX50_B2
RX50_A3
RX50_B3
Type
RRRRRRRR
Power-on
State
XXXXXXXX
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undened, rsvd=reserved for future use
The RX50_xy bits report the result of a receiver detection cycle. One bit is assigned for each channel of the device. RX50_xy is
at a logic 1 level indicating a load and receiver was detected. When RX50_xy is 0 then a load device was not detected. The RX50
register is read-only, and is undened after power-up until a Receiver Detection cycle completes.
Register Description
Byte 0 - Signal Detect (SIG)
SIG_xy=0=low input signal, SIG_xy=1=valid input signal
Bit
76543210
Name
SIG_A0
SIG_B0
SIG_A1
SIG_B1
SIG_A2
SIG_B2
SIG_A3
SIG_B3
Type
RRRRRRRR
Power-on
State
XXXXXXXX
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undened, rsvd=reserved for future use
The Signal Detect register provides information on the instantaneous status of the channel input from the Input Level Threshold
Detect circuit. If the input level falls below the Vth- level the relevant SIG_xy bit will be 0, indicating a low-level noise or electri-
cal idle input, resulting in the outputs going to the high-impedance off state or squelch mode. If the input level is above Vth-, then
SIG_xy is 1, indicating a valid input signal, and active signal recovery operation.
09-0002
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