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參數(shù)資料
| 型號(hào)： | PI4S708 |
| 英文描述： | Supervisory Circuits | 4.63V Reset Active Low/High Supervisor |
| 中文描述： | 監(jiān)控電路| 4.63V之間復(fù)位有源低/高監(jiān) |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大小： | 398K |
| 代理商： | PI4S708 |
4
PS8703 09/23/03
PI4S705, PI4S706x, PI4S707, PI4S708x, PI4S813L
μP Supervisor Circuts
Functional Description
The PI4S70xxx/813L family can assert reset output during power-up,
power-down and brownout conditions for uP system, detect power
failure or low-battery conditions with a 1.25V threshold detector and
have watchdog functions. Refer to Function Reference Table for their
individual features. For the typical application see Figure 4.
Reset Output
The supervisory circuits can assert reset for a microprocessor during
power-up, power-down and brownout to prevent code execution
errors.
On power-up, once V
CC
reaches about 1.2V, RESET is a guaranteed
logic low of 0.4V or less. As V
CC
rises, RESET stays low. When
V
CC
rises above the reset threshold, an internal timer releases
RESET after about 200ms. RESET pulses low whenever V
CC
drops below the reset threshold (brownout condition). If brownout
occurs in the middle of a previously initiated reset pulse, the pulse
continues for at least another 140ms.
On power-down, once V
CC
falls below the reset threshold, RESET
stays low and is guaranteed to be 0.4V or less until Vcc drops
below 1.2V.
The PI4S706xH, PI4S707, PI4S708x and PI4S813L active-high
RESET output is simply the complement of the RESET output,
and is guaranteed to be valid with V
CC
down to 1.2V. Some μPs,
such as Intel’s 80C51, require an active-high reset pulse.
Watchdog Timer
The watchdog circuit monitors the μP’s activity. If the μP does not
toggle the watchdog input (WDI) within 1.6sec and WDI is not in
high impedance, WDO goes low. As long as RESET is asserted or
the WDI input is in high impedance, the watchdog timer will stay
cleared and will not count. As soon as reset is released and WDI
is driven high or low, the timer will start counting. Pulses as short
as 50ns can be detected.
Typically, WDO will be connected to the non-maskable interrupt
input (NMI) of a μP. When V
CC
drops below the reset threshold,
WDO will go low whether or not the watchdog timer has timed
out yet. Normally this would trigger an NMI interrupt, but RESET
goes low simultaneously, and thus overrides the NMI interrupt. If
WDI is left unconnected, WDO can be used as a low-line output.
Since floating WDI disables the internal timer, WDO goes low
only when V
CC
falls below the reset threshold, thus functioning
as a low-line output.
Manual Reset
The manual-reset input (MR) allows reset to be triggered by a push-
button switch. The switch is effectively debounced by the 140ms
minimum reset pulse width. MR is TTL/CMOS logic compatible,
so it can be driven by any external logic line.
Power-Fail Comparator
The power-fail comparator will send out a low signal once detects
a voltage lowered than 1.25V. It can be used for various purposes
because its output and non-inverting input are not internally
connected. The inverting input is internally connected to a 1.25V
reference.
Typical Application Circuit
DC Linear
Regulator
Vcc
Supervisory
Circuit
PFI
WDI
WDO
PFO
μP
Vcc
RESET
I/O Line
NMI
Interrupt
IN
OUT
RESET
MR
μP
Unregulated DC
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| PI4S708S | Supervisory Circuits | 2.93V Reset Active Low Supervisor |
| PI4S708T | 12-Bit Rail-to-Rail Micropower DACs in SO-8; Package: SO; No of Pins: 8; Temperature Range: 0°C to +70°C |
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