參數(shù)資料
型號: PI4ULS5V102GAEX
廠商: Pericom
文件頁數(shù): 11/12頁
文件大?。?/td> 0K
描述: IC LOGIC TRANSLATOR
標(biāo)準包裝: 1
系列: ULS
邏輯功能: 電平移位器,雙向,3 態(tài)
位數(shù): 2
輸入類型: 電壓
輸出類型: 電壓
數(shù)據(jù)速率: 100Mbps
通道數(shù): 2
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 4ns
電源電壓: 1.2 V ~ 3.6 V,1.65 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-UFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 8-CSP(1.95x0.95)
包裝: 標(biāo)準包裝
其它名稱: PI4ULS5V102GAEXDKR
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12-12-0003
PT0334-3
12/18/12
8
PI4ULS5V102
2-Bit Universal Bi-directional Level
Shifter with Automatic Direction
Control & Advance Package Solution
Principles of operation
Applications
The
PI4ULS5V102
can
be
used
in
level-translation
applications for interfacing devices or systems operating at
different interface voltages with one another.
Architecture
The PI4ULS5V102 architecture(see Figure1) does not require
a direction-control signal to control the direction of data flow
from A to B or from B to A. In a dc state, the output drivers of
the PI4ULS5V102 can maintain a high or low, but are
designed to be weak, so that they can be overdriven by an
external driver when data on the bus starts flowing the
opposite direction.
The output one shots detect rising or falling edges on the A or
B ports. During a rising edge, the one shot turns on the PMOS
transistors (T1, T3) for a short duration, which speeds up the
low-to-high transition. Similarly, during a falling edge, the
one shot turns on the NMOS transistors (T2, T4) for a short
duration, which speeds up the high-to-low transition. The
typical output impedance during output transition is 70 Ω at
VCCO=1.2 V to 1.8 V, 50 Ω at VCCO=1.8 V to 3.3 V, and 40 Ω
at VCCO=3.3 V to 5 V.
Input Driver Requirements
Typical IIN vs VIN characteristics of the PI4ULS5V102 are
shown in Figure 2. For proper operation, the device driving
the data I/Os of the PI4ULS5V102 must have drive strength of
at least ±2mA.
Power Up
During operation, ensure that VCCA ≤ VCCB at all times. During
power-up sequencing, VCCA ≥ VCCB does not damage the
device, so any power supply can be ramped up first. The
PI4ULS5V102 has circuitry that disables all output ports
when either VCC is switched off (VCCA/B = 0 V).
Enable and Disable
The PI4ULS5V102 has an OE input that is used to disable the
device by setting OE = low, which places all I/Os in the high-
impedance (Hi-Z) state. The disable time (tdis) indicates the
delay between when OE goes low and when the outputs
acutally get disabled (Hi-Z). The enable time (ten) indicates
the amount of time the user must allow for the one-shot
circuitry to become operational after OE is taken high.
Pull-up or Pull-down Resistors on I/O Lines
The PI4ULS5V102 is designed to drive capacitive loads of up
to 70 pF. The output drivers of the PI4ULS5V102 have low dc
drive strength. If pullup or pulldown resistors are connected
externally to the data I/Os, their values must be kept higher
than 50 kΩ to ensure that they do not contend with the output
drivers of the PI4ULS5V102.
For the same reason, the PI4ULS5V102 should not be used in
applications such as I2C or 1-Wire where an open-drain driver
is connected on the bidirectional data I/O.
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