4
PS7030J
05/02/07
PI5C3390; PI5C32390
16:8 Multiplexer/Demultiplexer Bus Switch
Test
Disable LOW
Enable LOW
tPD
Switch
Closed
Open
Definitions:
CL = Load capacitance (includes jig and
probe capacitance)
RT = Termination resistance (should be
equal to ZOUT of the pulse generator)
Pulse
Generator
D.U.T.
VIN
RT
VOUT
CL
500
Ω
500
Ω
50pF
VCC
7V
Open
Test Circuit
Switch Position
Control
Input
Output
Normally
Low
Output
Normally
High
tPZL
tPLZ
0V
1.5V
3V
0V
1.5V
3V
0V
VOL
tPZH
3V
1.5V
Enable
Switch
GND
Disable
0.3V
VOH
0.3V
1. Input Control Enable = Low; Input Control Disable = High
2. Pulse Generator for all pulses:
Rate
<1.0 MHz; ZOUT <50Ω; tF, tR <2.5ns
Same Phase
Input Transisiton
Opposite Phase
Input Transisiton
tPLH
tPHL
0V
Output
VOH
VOL
3V
1.5V
0V
3V
1.5V
Enable and Disable Timing Diagram
Propagation Delay Diagram
Notes:
1. See test circuit and waveforms.
2. This parameter is guaranteed but not tested on Propagation Delays.
3. The bus switch contributes no propagational delay other than the RC delay of the On-Resistance of the switch and the load capacitance. The
time constant for the switch alone is of the order of 0.25ns for 50pF load. Since this time constant is much smaller than the rise/fall times of
typical driving signals, it adds very little propagational delay to the system. Propagational delay of the bus switch when used in a system is
determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
PI5C32390 Switching Characteristics over Operating Range
PI5C32390
Com
Parameters
Description
Conditions(1)
Min.
Typ.
Max.
Unit
tPLH
Propagation Delay(2,3)
CL = 50 pF
1.25
ns
tPHL
A, B to/from C
RL=500-ohm
tPZH
Bus Enable Time
1.5
6.5
ns
tPZL
AEN/BEN to A, B, C
tPHZ
Bus Disable Time
1.5
5.5
ns
tPLZ
AEN/BEN to A, B, C
07-0126