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PS8164B 03/15/99
PI6C104
for Desktop Pentium II
PCICLK_F/S1
PCICLK1
VSS
PCICLK3
PCICLK4
PCICLK2
PCICLK5
PCICLK6/PD#
VDD
48M/MODE
24M/REF/S2
VSS
VDD
VDD2
VDD2
CPUCLK0
CPUCLK1
VDD
VSS
SDATA
SCLK
S0
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
XTAL_IN
XTAL_OUT
VDD
APIC
REF1/P14
Pin Configuration
Block Diagram
Features
Up to 112 MHz operation
Spread Spectrum Modulation for CPUCLK, and PCICLK
Two copies of CPU clock with V
DD
of 2.5V ±5%
Seven copies of PCI clock,
(synchronous with CPU clock) 3.3V
One copy of Ref. clock @ 14.31818MHz (3.3V
TTL
)
48MHz USB Clock, 24MHz Super I/O clock
I
2
C Serial Configuration Interface
Low cost 14.31818MHz crystal oscillator input
Power management control
Isolated core V
DD
, V
SS
pins for noise reduction
28-pin SSOP (H) and SOIC package (S)
Description
The PI6C104 is a high-speed low-noise clock generator designed
to work with the PI6C18X family of clock buffer to meet all clock
needs for Desktop Intel Architecture platforms. CPU and chipset
clock frequencies from 66.6 MHz to 112 MHz are supported.
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers a portion of the I/O and the core. The 2.5V is used to power
the remaining outputs (CPU and APIC). 2.5V signaling follows
JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V
supplies is not required.
An asynchronous PD# signal may be used to orderly power down
(or up) the system during power on.
28-Pin
H, S
REF1
APIC
V
DDREF
V
DDAPIC
PCICLK[1:6]
CPUCLK[0:1]
REF
OSC
V
DDCPU
2
6
V
DDPCI
0,1
PCICLK_F
Div
PLL1
SEL
XTAL_OUT
XTAL_IN
S[0..2]
S
DATA
SCLOCK
I
2
C
PLL2
V
DDP
2
PI4
48MHz
24MHz/REF
MUX