參數(shù)資料
型號(hào): PI6C106
廠商: Pericom Semiconductor Corp.
英文描述: Pentium/Pro System Clock Chip
中文描述: 奔騰/ Pro系統(tǒng)時(shí)鐘芯片
文件頁(yè)數(shù): 4/8頁(yè)
文件大小: 370K
代理商: PI6C106
PI6C106
TM
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4
PS8546A 07/13/01
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internal by the PI6C106
prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD# is active
(low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power on latency is guaranteed
to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are dont care signals during
the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the PI6C106 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the PI6C106.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
CPUCLK
(Internal)
CPUCLK
(0:2)
PCICLK_E, PCICLK_F,
PCICLK (0:4)
REF, IOAPIC
INTERNAL
VCOs
INTERNAL
CRYSTAL OSC.
PCICLK
(Internal)
PD#
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