參數(shù)資料
型號(hào): PI6C180B
廠(chǎng)商: Pericom Semiconductor Corp.
英文描述: Precision 1-18 Clock Buffer
中文描述: 精密1-18時(shí)鐘緩沖器
文件頁(yè)數(shù): 5/7頁(yè)
文件大小: 573K
代理商: PI6C180B
PI6C180B
Precision 1-18 Clock Buffer
5
PS8468 05/03/00
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1.5V
1.5V
t
phl
t
plh
1.5V
1.5V
Input
Waveform
Output
Waveform
Output
Buffer
Test
Point
2.4
1.5
0.4
tSDKH
tSDKP
3.3V
Clocking
Interface
(TTL)
tSDKL
t
SDFALL
t
SDRISE
Test Load
Figure 1. Clock Waveforms
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500
resistor in parallel.
Minimum and Maximum Expected Capacitive Loads
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall
time are still within the specified values.
2. Minimize the number of vias of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
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a
o
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M
d
a
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a
M
s
U
s
N
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A
R
D
S
5
1
0
2
F
p
n
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S
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