參數(shù)資料
型號(hào): PI6C180VE
廠商: Pericom
文件頁數(shù): 5/7頁
文件大?。?/td> 0K
描述: IC CLK BUFF 1:18 100MHZ 48-SSOP
產(chǎn)品培訓(xùn)模塊: Total Timing Technology
標(biāo)準(zhǔn)包裝: 30
類型: 扇出緩沖器(分配)
電路數(shù): 1
比率 - 輸入:輸出: 1:18
差分 - 輸入:輸出: 無/無
輸入: TTL
輸出: TTL
頻率 - 最大: 100MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 48-SSOP
包裝: 管件
5
PS8141F
12/13/04
PI6C180
Precision 1-18 Clock Buffer
Figure 1. Clock Waveforms
Notes:
1. Maximum rise/fall times are guaranteed at maximum
specified load.
2. Minimum rise/fall times are guaranteed at minimum
specified load.
3. Rise/fall times are specified with pure capacitive
load as shown.
Testing is done with an additional 500-ohm resistor
in parallel.
Minimum & Maximum Expected
Capacitive Loads
Clock
Min.
Load
Max.
Load Units
Notes
SDRAM
20
30
pF
SDRAM DIMM
Specfication
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to
the respective clock pins. Typical value for CI is 10pF. Series
resistor value can be increased to reduce EMI provided that
the rise and fall time are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over
a continuous power plane. Avoid routing clock traces from
plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables
or any external connectors.
1.5V
tphl
tplh
1.5V
Input
Waveform
Output
Waveform
Output
Buffer
Test
Point
2.4
1.5
0.4
tSDKH
tSDKP
3.3V
Clocking
Interface
(TTL)
tSDKL
tSDFALL
tSDRISE
Test Load
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