參數(shù)資料
型號(hào): PI6C20800VE
廠商: Pericom Semiconductor Corp.
英文描述: 1:8 Clock Driver for Intel PCI Express Chipsets
中文描述: 1:8時(shí)鐘驅(qū)動(dòng)器,英特爾的PCI Express芯片組
文件頁數(shù): 2/10頁
文件大小: 269K
代理商: PI6C20800VE
2
PS8746C 02/01/06
PI6C20800
1:8 Clock Driver for Intel
PCI Express Chipsets
Pin Descriptions
Pin Name
Type
Pin #
Descriptions
SRC_DIV#
Input
1
3.3V LVTTL input for selecting input frequency divide by 2,
active LOW.
0.7V Differential SRC input from PI6C410 clock synthesizer
SRC & SRC#
Input
4, 5
OE [0:7]
Input
6, 7, 14, 15, 35, 36,
43, 44
3.3V LVTTL input for enabling outputs, active HIGH.
OE_INV
Input
40
3.3V LVTTL input for inverting the OE, SRC_STOP# and
PWRDWN# pins.
When 0 = same stage
When 1 = OE[0:7], SRC_STOP#, PWRDWN# inverted.
OUT[0:7] & OUT[0:7]#
Output
8, 9, 12, 13, 16 17,
20, 21, 29, 30, 33, 34,
37, 38, 41, 42
22
23
24
46
27
28
26
0.7V Differential outputs
PLL/BYPASS#
SCLK
SDA
I
REF
SRC_STOP#
PLL_BW#
PWRDWN#
Input
Input
I/O
Input
Input
Input
Input
3.3V LVTTL input for selecting fan-out of PLL operation.
SMBus compatible SCLOCK input
SMBus compatible SDATA
External resistor connection to set the differential output current
3.3V LVTTL input for SRC stop, active LOW
3.3V LVTTL input for selecting the PLL bandwidth
3.3V LVTTL input for Power Down operation, active LOW
3.3V LVTTL output, transition high when PLL lock is achieved
(Latched output)
3.3V Power Supply for Outputs
Ground for Outputs
Ground for PLL
3.3V Power Supply for PLL
LOCK
Output
45
V
DD
V
SS
V
SS_A
V
DD_A
Power
Ground
Ground
Power
2, 11, 19, 31, 39
3, 10, 18, 25, 32
47
48
Serial Data Interface (SMBus)
PI6C20800 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit
address and read/write bit as shown below.
Address assignment
A6
1
A5
1
A4
0
A3
1
A2
1
A1
1
A0
0
R/W
0/1
Data Protocol
(1)
1 bit
7 bits
1
1
8 bits
1
8 bits
Byte
Count
= N
1
8 bits
1
8 bits
Data
Byte N
- 1
1
1 bit
Start
bit
Slave
Addr
R/W
Ack
Register
offset
Ack
Ack
Data
Byte 0
Ack
Ack
Stop
bit
Note:
1.
Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
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