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參數(shù)資料
| 型號： | PI6C2502W |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | SMBus Dual High-SideSwitch Controller; Package: MSOP; No of Pins: 8; Temperature Range: 0°C to +70°C |
| 中文描述： | 單時鐘驅(qū)動器|的CMOS |?？苵 8引腳|塑料 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 371K |
| 代理商： | PI6C2502W |
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PS8382B 03/20/02
Product Pin Configuration
Logic Block Diagram
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PI6C2502
Product Description
The PI6C2502 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the feedback FB_OUT output
to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero.
Product Features
High-Performance Phase-Locked-Loop Clock Distribution
for Networking,
Synchronous DRAM modules for server/workstation/
PC applications
Allows Clock Input to have Spread Spectrum
modulation for EMI reduction
Zero Input-to-Output delay
Low jitter: Cycle-to-Cycle jitter ±100ps max.
On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
Operates at 3.3V V
CC
Wide range of Clock Frequencies up to 80 MHz
Package: Plastic 8-pin SOIC Package (W)
8-Pin
W
Phase-Locked Loop Clock Driver
Application
If a system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers such as
PI6C2509Q, and PI6C2510Q, is likely to be impractical. The
device-to-device skew introduced can significantly reduce the
performance. Pericom recommends the use of a zero-delay buffer
and an eighteen output non-zero-delay buffer. As shown in Figure
1, this combination produces a zero-delay buffer with all the signal
characteristics of the original zero-delay buffer, but with as many
outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Figure 1. This Combination Provides Zero-Delay Between the
Reference Clocks Signal and 17 Outputs
CLK_IN
FB_IN
PLL
AV
CC
FB_OUT
CLK_OUT
1
2
3
V
CC
4
CLK_OUT
CLK_IN
GND
FB_IN
8
7
6
5
AGND
FB_OUT
AV
CC
17
Zero Delay
Buffer
PI6C2502
Reference
Clock
Signal
CLK_OUT
Feedback
18 Output
Non-Zero
Delay
Buffer
V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI6C2504A | Phase-Locked Loop Clock Driver with 4 Clock Outputs |
| PI6C2504AQ | Phase-Locked Loop Clock Driver with 4 Clock Outputs |
| PI6C2504Q | Phase-Locked Loop Clock Driver with 4 Clock Outputs |
| PI6C2510-133 | Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs |
| PI6C2516 | Phase-Locked Loop Clock Driver with 16 Clock Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6C2502WE | 功能描述:鎖相環(huán) - PLL 3.3v PLL Clock Drivr RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C2502WEX | 功能描述:鎖相環(huán) - PLL 3.3v PLL Clock Drivr RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C2504 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:Phase-Locked Loop Clock Driver with 4 Clock Outputs |
| PI6C2504A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:Phase-Locked Loop Clock Driver with 4 Clock Outputs |
| PI6C2504AQ | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:Phase-Locked Loop Clock Driver with 4 Clock Outputs |
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