Programmable Skew Clock Buffer - SuperClock 1" />
參數(shù)資料
型號: PI6C39911JE
廠商: Pericom
文件頁數(shù): 2/11頁
文件大?。?/td> 0K
描述: IC PROG SKEW CLOCK DRIVER 32PLCC
產(chǎn)品變化通告: Product Discontinuation 03/Oct/2011
標準包裝: 32
系列: SuperClock®
類型: 時鐘緩沖器
PLL:
輸入: LVTTL
輸出: LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 1:8
差分 - 輸入:輸出: 無/無
頻率 - 最大: 133MHz
除法器/乘法器: 是/是
電源電壓: 2.97 V ~ 3.63 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-LCC(J 形引線)
供應商設備封裝: 32-PLCC(11.43x13.97)
包裝: 管件
PI6C39911
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer - SuperClock
10
PS8497I
11/06/08
Figure 8. Board-to-Board Clock Distribution
Figure8showsthePI6C39911 connectedinseriestoconstructazero
skew clock distribution tree between boards. Delays of the down
stream clock buffers can be programmed to compensate for the wire
length (i.e., select negative skew equal to the wire delay) necessary
to connect them to the master clock source, approximating a zero-
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
System
Clock
REF
LOAD
Z0
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
Z0
LOAD
Z0
L1
L2
L3
L4
PI6C3991
1
delay clock tree. Cascaded clock buffers will accumulate low
frequency jitter because of the non-ideal filtering characteristics of
thePLLfilter.Itisrecommendedthatnotmorethantwoclockbuffers
be connected in series.
08-0298
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