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參數(shù)資料
| 型號： | PI6C3991JE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROG SKEW CLOCK DRIVER 32PLCC |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 32 |
| 系列： | SuperClock® |
| 類型： | 時(shí)鐘緩沖器 |
| PLL： | 是 |
| 輸入： | LVTTL |
| 輸出： | LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 80MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 32-PLCC（11.43x13.97） |
| 包裝： | 管件 |
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PI6C3991
3.3V High-Speed, Low-Voltage Programmable
Skew Clock Buffer - SuperClock
9
PS8450D
11/12/08
Figure 6. Frequency Divider Connections
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
20 MHz
10 MHz
5 MHz
20 MHz
Figure 6 demonstrates the SuperClock in a clock divider application.
2Q0 is fed back to the FB input and programmed for zero skew. 3Qx
isprogrammedtodividebyfour.4Qxisprogrammedtodividebytwo.
Note that the rising edges of the 4Qx and 3Qx outputs are aligned.
The 1Qx outputs are programmed to zero skew and are aligned with
the 2Qx outputs. In this example, the FS input is grounded to
configure the device in the 15 to 30 MHz range since the highest
frequency output is running at 20 MHz.
Figure 7 shows some of the functions that are selectable on the 3Qx
and 4Qx outputs. These include inverted outputs and outputs that
offer divide-by-2 and divide-by-4 timing. An inverted output allows
the system designer to clock different sub-systems on opposite
edges, without suffering from the pulse asymmetry typical of non-
ideal loading. This function allows the two subsystems to each be
clocked 180 degrees out of phase, but still to be aligned within the
skew spec.
The divided outputs offer a zero-delay divider for portions of the
system that need the clock to be divided by either two or four, and
still remain within a narrow skew of the “1X” clock. Without this
feature, an external divider would need to be add-ed, and the
propagation delay of the divider would add to the skew between the
different clock signals.
These divided outputs, coupled with the Phase Locked Loop, allow
the SuperClock to multiply the clock rate at the REF input by either
two or four. This mode will enable the designer to distribute a low-
frequency clock between various portions of the system, and then
locallymultiplytheclockratetoamoresuitablefrequency,whilestill
maintaining the low-skew characteristics of the clock driver. The
SuperClock can perform all of the functions described above at the
same time. It can multiply by two and four or divide by two (and four)
at the same time that it is shifting its outputs over a wide range or
maintaining zero skew between selected outputs.
Figure 7. Multi-Function Clock Driver
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
20 MHz
Distribution
Clock
REF
LOAD
Z0
80 MHz
Inverted
20 MHz
80 MHz
Zero Skew
80 MHz Skewed
–3.125ns (–4tU)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6C3991JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver |
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| PI6C3Q991-2J | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3.3V Programmable Skew PLL Clock Driver |
| PI6C3Q991-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock IC | 500ps Accuracy. 3.3V. Balanced. 3.75 to 85 MHz |
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