參數(shù)資料
型號(hào): PI6C41204ALE
廠商: Pericom
文件頁(yè)數(shù): 6/11頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK BUFFER MUX 2:4 20-TSSOP
產(chǎn)品變化通告: Product Discontinuation 09/Dec/2010
標(biāo)準(zhǔn)包裝: 74
類型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 無(wú)/是
輸入: LVCMOS,LVTTL
輸出: LVPECL
頻率 - 最大: 266MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
4
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PS8626E
11/14/08
PI6C4120x
LVCMOS to LVPECL Driver
s
t
u
p
n
Is
t
u
p
t
u
O
N
E
_
K
L
CL
E
S
_
K
L
Ce
c
r
u
o
S
d
e
t
c
e
l
e
S*
3
Q
u
r
h
t
0
Q*
3
Q
n
u
r
h
t
0
Q
n
00
0
K
L
CW
O
L
;
d
e
l
b
a
s
i
DH
G
I
H
;
d
e
l
b
a
s
i
D
01
1
K
L
CW
O
L
;
d
e
l
b
a
s
i
DH
G
I
H
;
d
e
l
b
a
s
i
D
10
0
K
L
Cd
e
l
b
a
n
Ed
e
l
b
a
n
E
11
1
K
L
Cd
e
l
b
a
n
Ed
e
l
b
a
n
E
Table 3a. Control Input Function Table
After CLK_EN switches, the clock outputs are disabled or enabled following
a rising and falling input clock edge as shown in figure1. In the active mode, the state
of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3b.
Disabled
Enabled
CLK0, CLK1
CLK_EN
nQ0 - nQ3*
Q0 - Q3*
Figure 1. CLK_EN Timing Diagram
Table 3b. Clock Input Function Table
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1
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C
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0
K
L
C*
3
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0
Q*
3
Q
n
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0
Q
n
0W
O
LH
G
I
H
1H
G
I
HW
O
L
Note:
*PI6C41204 and PI6C41204A have four differential outputs. Q0 through Q3 and nQ0 through nQ3.
PI6C41202 has two differential outputs. Q0 through Q1 and nQ0 through nQ1.
08-0298
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