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參數(shù)資料
| 型號： | PI6CV857L |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | PLL Clock Driver for 2.5V DDR-SDRAM Memory |
| 中文描述： | PLL時鐘驅(qū)動器2.5V的DDR - SDRAM內(nèi)存 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 340K |
| 代理商： | PI6CV857L |
1
PS8543 06/11/01
V
DDQ
1
2
3
4
5
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9
10
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12
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48
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34
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32
31
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27
26
25
FBOUT
FBOUT
GND
Y5
GND
Y7
GND
FBIN
V
DDQ
FBIN
PWRDWN
GND
Y8
GND
Y9
Y8
V
DDQ
Y7
V
DDQ
Y6
Y6
Y5
V
DDQ
Y9
GND
Y0
Y0
GND
Y3
GND
Y1
Y1
V
DDQ
V
DDQ
CLK
CLK
V
DDQ
AV
DD
V
DDQ
GND
Y2
Y2
GND
Y3
Y4
Y4
AGND
Product Description
PI6CV857L PLL clock device is developed for registered DDR DIMM
applications This PLL Clock Buffer is designed for 2.5 V
DDQ
and 2.5V
AV
DD
operation and differential data input and output levels.
Package options include plastic Thin Shrink Small-Outline Package
(TSSOP).The device is a zero delay buffer that distributes a differ-
ential clock input pair (CLK, CLK) to ten differential pairs of clock
outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock
outputs (FBOUT,FBOUT) . The clock outputs are controlled by the
input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V
LVCMOS input (PWRDWN) and the Analog Power input (AV
DD
).
When input PWRDWN is low while power is applied, the input
receivers are disabled, the PLL is turned off and the differential clock
outputs are 3-stated. When the AV
DD
is strapped low, the PLL is
turned off and bypassed for test purposes.
When the input frequency falls below a suggested detection fre-
quency that is below the operating frequency of the PLL, the device
will enter a low power mode. An input frequency detection circuit will
detect the low frequency condition and perform the same low power
features as when the PWRDWN input is low.
The PLL in the PI6CV857L clock driver uses the input clocks (CLK,
CLK) and the feedback clocks (FBIN,FBIN) to provide high-perfor-
mance, low-skew, low-jitter output differential clocks (Y[0:9], Y[0:9]).
The PI6CV857L is also able to track Spread Spectrum Clocking for
reduced EMI.
Product Features
PLL clock distribution optimized for Double Data Rate
SDRAM applications.
Distributes one differential clock input pair to ten differential
clock output pairs.
Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
Input PWRDWN: LVCMOS
Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the clock input.
Operates at AV
DD
= 2.5V for core circuit and internal PLL,
and V
DDQ
= 2.5V for differential output drivers
Available Packages: Plastic 48-pin TSSOP
Block Diagram/Pin Configuration
PLL Clock Driver for
2.5V DDR-SDRAM Memory
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Y0
Y0
Y1
PWRDWN
AVDD
FBIN
FBIN
CLK
CLK
PLL
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
Powerdown
and Test
Logic
48-Pin
A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6CV857LA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:PLL Clock Driver for 2.5V DDR-SDRAM Memory |
| PI6CV857LAE | 功能描述:鎖相環(huán) - PLL 170 MHZ 1:10 SSTV Clock Driver RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CV857LAEX | 功能描述:鎖相環(huán) - PLL 170 MHZ 1:10 SSTV Clock Driver RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CV857LK | 制造商:Pericom Semiconductor Corporation 功能描述:170 MHZ 1:10 SSTV CLOCK DRIVER - Rail/Tube |
| PI6CV857LKE | 功能描述:鎖相環(huán) - PLL 170 MHZ 1:10 SSTV Clock Driver RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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