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參數(shù)資料
| 型號： | PI74FCT162511T |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | Fast CMOS 16-Bit Registered/Latched Transceiver With Parity |
| 中文描述： | 快速CMOS 16位注冊/鎖存校驗器 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 87K |
| 代理商： | PI74FCT162511T |
4
PS2080A 01/15/95
PI74FCT16511/162511T
16-BIT REGISTERED/
LATCHED TRANSCEIVER WITH PARITY
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Truth Table
(1,2)
Output
Buffers
B
X
Z
L
H
L
H
B
(3)
B
(4)
Inputs
OEAB
H
L
L
L
L
L
L
LEAB
X
H
H
L
L
L
L
CLKAB
X
X
X
↑
↑
L
H
A
X
X
L
H
L
H
X
X
NOTES:
1.
H = High Voltage Level
L = Low Voltage Level
X = Don't Care or Irrelevant
Z = High Impedance
↑
= LOW-to-HIGH Transition
A-to-B data flow is shown. B-to-A flow control is the same, except using
OEBA, LEBA, and CLKBA.
Output level before the indicated steady-state input conditions were
established.
Output level before the indicated steady-state input conditions were
established, assuming CLKAB was HIGH before LEAB went LOW.
2.
3.
4.
Truth Table (Parity Generation)
(1, 2, 3, 4, 5)
A
0
- A
7
, Total Number of Inputs that are high
ODD/EVEN
PB
1
1, 3, 5 or 7
L
H
1, 3, 5 or 7
H
L
0, 2, 4, 6 or 8
L
L
0, 2, 4, 6 or 8
H
H
NOTES:
1. Conditions shown are for GEN/CHK = L, OEAB = L, OEBA = H.
2. A-to-B parity generation is shown. B-to-A can check parity while A-to-B is performing generation. B-to-A will not generate parity.
3. The response shown is for LEAB = H. If LEAB = L, then CLKAB will control as an edge triggered clock.
4. Conditions shown are for the byte A0-A7. The byte A8-A15 is similar but will output the parity on PB
2
.
5. The error flag PERB will remain in a high state during parity generation.
Truth Table (Parity Checking)
(1, 2, 3, 4)
A
0
- A
7
and PA
1
(5)
, Total Number of Inputs that are high
ODD/EVEN
PERB
1, 3, 5, 7 or 9
L
L
1, 3, 5, 7 or 9
H
H
(6)
0, 2, 4, 6 or 8
L
H
(6)
0, 2, 4, 6 or 8
H
L
NOTES:
1. Conditions shown are for GEN/CHK = H, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A parity checking is same but uses OEBA = L, OEAB = H and errors will be indicated on PERA.
3. In parity checking mode the parity bits will be transmitted unchanged along with the corresponding data regardless of parity errors. (PB
1
= PA
1
)
4. The response shown is for LEAB = H. If LEAB = L, then CLKAB will control as an edge triggered clock.
5. Conditions shown are for the byte A0-A7 and PA
1
. The byte A8-A15 and PA
2
is same.
6. The parity error flag PERB is a combined flag for both bytes A0-A7 and A8-A15. If a parity error occurs on either byte PERB will go low.
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