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PI74FCT16240/162240/162H240T
16-BIT BUFFER/LINE DRIVERS
1
PS2030A 03/11/96
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Product Description:
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-
duced in the Company’s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT16240T, PI74FCT162240T, and PI74FCT162H240T
are inverting 16-bit buffer/line drivers designed for applications
driving high capacitance loads and low impedance backplanes.
These high-speed, low power devices offer bus/backplane interface
capability and a flow-through organization for ease of board layout.
These devices are designed with three-state controls to operate in
a Quad-Nibble, Dual-Byte, or a single 16-bit word mode.
The PI74FCT16240T output buffers are designed with a Power-
Off disable allowing “l(fā)ive insertion” of boards when used as
backplane drivers.
The PI74FCT162240T has ±24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H240T has “Bus Hold” which retains the input's
last state whenever the input goes to high-impedance preventing
“floating” inputs and eliminating the need for pull-up/down resistors.
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Logic Block Diagram
Product Features:
Common Features:
PI74FCT16240T, PI74FCT162240T, and PI74FCT162H240T
are high-speed,
low power devices with high current drive
V
CC
= 5 V ±10%
Hysteresis on all inputs
Packages available:
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 300 mil wide plastic SSOP (V)
PI74FCT16240T Features:
High output drive: I
OH
= –32 mA; I
OL
= 64 mA
Power off disable outputs permit "live insertion"
Typical V
OLP
(Output Ground Bounce) < 1.0V
at V
CC
= 5V, T
A
= 25°C
PI74FCT162240T Features:
Balanced output drivers: ±24 mA
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V
at V
CC
= 5V, T
A
= 25°C
PI74FCT162H240T Features:
Bus Hold retains last active bus state during 3-state
Eliminates the need for external pull-up resistors
Buffer/Line Drivers
1
OE
1
A
0
1
Y
0
1
A
1
1
Y
1
1
A
2
1
Y
2
1
A
3
1
Y
3
3
OE
3
A
0
3
Y
0
3
A
1
3
Y
1
3
A
2
3
Y
2
3
A
3
3
Y
3
2
OE
2
A
0
2
Y
0
2
A
1
2
Y
1
2
A
2
2
Y
2
2
A
3
2
Y
3
4
OE
4
A
0
4
Y
0
4
A
1
4
Y
1
4
A
2
4
Y
2
4
A
3
4
Y
3