![](http://datasheet.mmic.net.cn/260000/PI74FCT162511_datasheet_15942081/PI74FCT162511_3.png)
3
PS2080A 01/15/95
PI74FCT16511/162511T
16-BIT REGISTERED/
LATCHED TRANSCEIVER WITH PARITY
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Product Pin Description
Pin Name
Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
CLKAB
A-to-B Clock Input
CLKBA
B-to-A Clock Input
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
PERA
Parity Error (Open Drain) on A Outputs
PERB
Parity Error (Open Drain) on B Outputs
Ax
A-to-B Data Inputs or B-to-A 3-State Outputs
Bx
B-to-A Data Inputs or B-to-A 3-State Outputs
ODD/EVEN
(1)
Parity Mode Selection Input
GEN/CHK
(1)
A-to-B Port Generate or Check Mode Input
PAx
(2)
A-to-B Parity Input, B-to-A Parity Output
PBx
B-to-A Parity Input, A-to-B Parity Output
GND
Ground
V
CC
Power
NOTES:
1. ODD/EVEN and GEN/CHK should be tied to V
CC
or GND with no resistor
for optimum results.
2. The PAx pin input is internally disabled during parity generation. This means
that when generating parity in the A-to-B direction, there is no need to add a
pull-up resistor to guarantee state. The pin will still function properly as the
parity output for the B-to-A direction.
Product Pin Configuration
Capacitance
(T
A
= 25°C, f = 1 MHz)
Parameters
(1)
C
IN
C
I
/
O
C
O
Description
Input Capacitance
I/O Capacitance
Open Drain Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
V
OUT
= 0V
Typ
4.5
5.5
4.5
Max.
6.0
8.0
6.0
Units
pF
pF
pF
Note:
1. This parameter is determined by device characterization but is not production tested.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEAB
LEAB
PA
1
GND
A
0
A
1
VCC
A
2
A
3
A
4
A
5
A
6
A
7
GND
PERA
A
8
A
9
A
10
A
11
A
12
A
13
V
CC
A
14
A
15
GND
PA
2
OEBA
LEBA
GENCHK
CLKAB
PB
1
GND
B
0
B
1
VCC
B
2
B
3
B
4
B
5
B
6
B
7
PERB
GND
B
8
B
9
B
10
B
11
B
12
B
13
V
CC
B
14
B
15
GND
PB
2
CLKBA
ODD/EVEN
56-PIN
V56
A56