參數(shù)資料
型號(hào): PI74SSTV16857AE
廠商: Pericom
文件頁(yè)數(shù): 6/7頁(yè)
文件大?。?/td> 0K
描述: IC REG BUFFER 14BIT 48TSSOP
產(chǎn)品變化通告: Product Discontinuation 25/Apr/2012
標(biāo)準(zhǔn)包裝: 39
系列: 74SSTV
邏輯類(lèi)型: DDR 的寄存緩沖器
電源電壓: 2.3 V ~ 2.7 V
位數(shù): 14
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 管件
6
PS8460H
11/10/08
PI74SSTV16857
14-Bit Registered Buffer
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Voltage and Current Waveforms
InputActiveandInactiveTimes
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Setup and Hold Times
Test Circuit and Switching Waveforms
Notes:
8.
CL includes probe and jig capacitance.
9.
IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA.
10. All input pulses are supplied by generators having the following characteristics:
PRR
≤10 MHz, ZO = 50Ω. Input slew rate = 1V/ns ±20% (unless otherwise specified).
11. The outputs are measured one at a time with one transition per measurement.
12. VTT = VREF = VDDQ/2
13. VIH = VREF + 350mV (ac voltage levels) for SSTL inputs. VIH = VDD for LVCMOS input.
14. VIL = VREF + 350mV (ac voltage levels) for SSTL inputs. VIL = GND for LVCMOS input.
15. tPLH and tPHL are the same as tpd.
Parameter Measurement Information (VDD = 2.5V ±0.2V)
LoadCircuit
Input
VIL
VREF
tw
VIH
Input
Timing
Input
th
tsu
VIL
VICR
VREF
VI(PP)
VIH
Voltage Waveforms - Propagation Delay Times
Timing
Input
Output
VICR
tPLH
tPHL
VICR
VI(PP)
VOH
VTT
VOL
LVCMOS
RESET
Input
Output
tPHL
VDD/2
VOH
VIH
VIL
VTT
VOL
Voltage Waveforms - Propagation Delay Times
VTT
RL = 50Ω
From Output
Under Test
CL = 30pF(8)
Test Point
LVCMOS
RESET
Input
IDD(9)
VDD
VDD/2
tinact
0V
IDDH
10%
90%
IDDL
tact
08-0291
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