- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1962 > PI7C9X20404GPBNBE (Pericom)IC PCIE PACKET SWITCH 148LFBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | PI7C9X20404GPBNBE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 5/79頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 148LFBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 189 |
| 系列： | GreenPacket™ |
| 應(yīng)用： | 封裝開(kāi)關(guān)，4 端口/4 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 148-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 148-LFBGA（12x12） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 13 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
3.3
HOT PLUG SIGNALS
NAME
PIN
TYPE
DESCRIPTION
PWR_IND [3:1]
N5, M5, L3
O
Power Indicator: Indicates the power status for each slot at
downstream port. PWR_IND [x] is correspondent to Port x, where
x=1,2,3. They are active-high signals. The pins have internal pull-
down.
ATT_IND [3:1]
M1, N1, N2
O
Attention Indicator: Indicates the attention status for each slot at
downstream port. ATT_IND [x] is correspondent to Port x, where
x=1,2,3. They are active-high signals. ATT_IND[3:2] have internal
pull-down.
ATT_BTN [3:1]
K3, K2, K1
I
Attention Button: When asserted high, it represents the attention
button has been pressed for the slot at the downstream port. ATT_BTN
[x] is correspondent to Port x, where x=1,2,3.
MRL_PDC [3:1]
N7, M7, J1
I
Presence Detected Change: When asserted low, it represents the
device is present in the slot of downstream ports. Otherwise, it
represents the absence of the device. MRL_PDC [x] is correspondent
to Port x, where x=1,2,3.
PWR_ENA_L [3:1]
P2, J2, H1
O
SLOT Power Enable (Active LOW): Indicates the enable status of
the power connecting to the associated slot. PWR_ENA [x] is
correspondent to Portx, where x=1,2,3. They are active-low signals.
Pins are set to “000” by default.
PWR_FLT [3:1]
N8, M8, P4
I
SLOT Power Fault: When asserted high, it indicates a power fault on
one or more supply rails. PWR_FLT [x] is correspondent to Port x,
where x=1,2,3.
3.4
MISCELLANEOUS SIGNALS
NAME
PIN
TYPE
DESCRIPTION
EECLK
P8
O
EEPROM Clock: Clock signal to the EEPROM interface.
EEPD
M9
I/O
EEPROM Data: Bi-directional serial data interface to and from the
EEPROM. The pin has internal pull-up.
SMBCLK
N4
I
SM Bus Clock: System management Bus Clock. Pin has an internal
pull-down.
SMBDATA
L2
I/O
SM Bus Data: Bi-Directional System Management Bus Data.
SCAN_EN
P10
I/O
Full-Scan Enable Control: For normal operation, SCAN_EN is an
output with a value of “0”. SCAN_EN becomes an input during
manufacturing testing.
PORTERR [3:0]
N9, P7, P6,
P5
O
Port PHY Error Status: These pins are used to display the PHY Error
status of the ports. When PORTERR is flashing (alternating high and
low signals), it indicates that a PHY error is detected. When it is low,
no PHY error is detected. PORTERR [x] is correspondent to Port x,
where x=0,1,2,3.
GPIO [7:0]
F1, E1, G2,
G3, D1, C1,
F2, E2
I/O
General Purpose Input and Output: These eight general-purpose
pins are programmed as either input-only or bi-directional pins by
writing the GPIO output enable control register.
When SMBus is implemented, GPIO[7:5] act as the SMBus address
pins, which set Bit 2 to 0 of the SMBus address.
TEST1
G1
I
Test1: This pin is for internal test purpose. Test1 should be tied to
ground through a pull-down resistor.
TEST2
TEST3
TEST4
TEST5
C3
C6
B6
A6
I
Test2/3/4/5: These pins are for internal test purpose. Test2, Test3,
Test4 and Test5 should be tied to 3.3V through a pull-up resistor.
TEST6
B11
I
Test6: This pin is for internal test purpose. Test6 should be connected
an (475 ohm +/- 1%) external resistor to Vss.
TEST7
M6
I
Test7: This pin is for internal test purpose. Test7 should be tied to
ground through a pull-down resistor (5.1k ohm).
NC
A10, A12,
A14, B10,
B12, B14,
H3, L1, M2,
M3, M4, N3
Not Connected: These pins can be just left open.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C9X20404SLCFDE | IC PCIE PACKET SWITCH 128LQFP |
| PI7C9X20505GPBNDE | IC PCIE PACKET SWITCH 256BGA |
| PI7C9X20508GPBNDE | IC PCIE PACKET SWITCH 256BGA |
| PI7C9X440SLBFDE | IC PCIE-TO-USB 2.0 CTRLR 128LQFP |
| PI7C9X442SLBFDE | IC PCIE-TO-USB2.0 SWIDGE 128LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C9X20404SLCEVB | 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20404SLCFDE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20404SLCFDEX | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20505GPBNDE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 5port 5lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20508GPANDE | 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。