參數(shù)資料
型號(hào): PI90SD1636A
廠商: Pericom Semiconductor Corp.
英文描述: SERDES Gigabit Ethernet Transceiver
中文描述: SERDES的千兆以太網(wǎng)收發(fā)器
文件頁(yè)數(shù): 9/15頁(yè)
文件大?。?/td> 559K
代理商: PI90SD1636A
9
PS8641 10/14/04
PI90SD1636A
SERDES Gigabit Ethernet Transceiver
Table 9. Receiver Timing Characteristics
T
A
= 0°C to +70°C, V
CC
= 3.15V to 3.45V
Symbol
Parameter
b_sync
[1]
Bit Sync Time
f_lock
Frequency Lock at Powerup
t
SETUP
Data Setup Before Rising Edge of RX_CLK
t
HOLD
Data Hold After Rising Edge of RX_CLK
t
DUTY
RX_CLK Duty Cycle
t
A-B
RX_CLK Skew
Min.
Typ.
Max.
2500
500
Unit
bits
μ
s
2.5
1.5
40
7.5
ns
60
8.5
%
ns
ns
bits
T_rxlat
[2]
Receiver Latency
22.4
28.0
DATA
DATA
DATA
TX<9:0>
TX_CLK
t
HOLD
t
SETUP
1.4V
2.0V
0.8V
DATA
DATA
Figure 3. Transmitter Section Timing
T5
T6
T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5
DATA BYTE A
DATA BYTE B
DATA BYTE B
DATA BYTE C
1.4V
DOUT±
TX<9:0>
TX_CLK
t_TXLAT
Figure 4. Transmitter Latency
Notes:
1.
2.
This is the recovery for input phase jumps.
The receiver latency as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the
first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, either RBC1 or
RBC0).
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