參數(shù)資料
型號: PI90SD1636AFD
廠商: Pericom Semiconductor Corp.
英文描述: SERDES Gigabit Ethernet Transceiver
中文描述: SERDES的千兆以太網(wǎng)收發(fā)器
文件頁數(shù): 8/15頁
文件大?。?/td> 559K
代理商: PI90SD1636AFD
8
PS8641 10/14/04
PI90SD1636A
SERDES Gigabit Ethernet Transceiver
Table 6. DC Electrical Characteristics
T
A
= 0°C to +70°C, V
CC
= 3.15V to 3.45V
Symbol
Parameter
V
IH,TTL
TTL Input High Voltage Level, Guaranteed High Signal for All Inputs
V
IL,TTL
TTL Input Low Voltage Level, Guaranteed Low Signal for All Inputs
V
OH,TTL
TTL Output High Voltage Level, I
OH
= -400 mA
V
OL,TTL
TTL Output Low Voltage Level, I
OL
= 1 mA
I
IH,TTL
Input High Current, V
IN
= 2.4 V, V
CC
= 3.45 V
I
IL,TTL
Input Low Current, V
IN
= 0.4 V, V
CC
= 3.45 V
I
CC,TRX[1,2]
Transceiver V
CC
Supply Current, TA = 25°C
Min.
2
0
2.2
0
Typ.
Max.
5.5
0.8
V
CC
0.6
40
-600
Unit
V
μA
220
mA
Notes:
1. Measurement Conditions: Tested sending 1250 MBd PRBS 2
7
-1 sequence from a serial Bit Error Rate Tester (BERT) with DOUT± outputs
terminated with 150 resistors to GND.
2. Typical values are at V
CC
= 3.3 volts.
Table 7. Transceiver Reference Clock Requirements
T
A
= 0°C to +70°C, V
CC
= 3.15V to 3.45V
Symbol
Parameter
f
Nominal Frequency (for gigabit Ethernet Compliance)
F
tol
Frequency Tolerance
Symm
Symmetry (Duty Cycle)
Tj
Peak-to-Peak Jitter
Min.
Typ.
125
Max.
Unit
MHz
ppm
%
ps
-100
40
+100
60
80
Table 8.
Transmitter Timing Characteristics
T
A
= 0
°
C to +70
°
C, V
CC
= 3.15V to 3.45V
Symbol
Parameter
t
setup
Setup Time to Rising Edge of TX_CLK
t
hold
Hold Time to Rising Edge of TX_CLK
Min.
1.5
1.0
Typ.
Max.
Unit
ns
t_txlat
[1]
Transmitter Latency
3.5
4.4
bits
Note:
1.
The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising
edge of the transmit by clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the rising edge of the first bit
transmitted).
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