參數(shù)資料
型號: PIC10F204-I/P
廠商: Microchip Technology
文件頁數(shù): 71/94頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 256X12 8DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 60
系列: PIC® 10F
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 3
程序存儲器容量: 384B(256 x 12)
程序存儲器類型: 閃存
RAM 容量: 16 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 637 (CN2011-ZH PDF)
配用: AC103003-ND - BOARD DEMO PIC10F CAP TOUCH
AC162059-ND - HEADER INTRFC MPLAB ICD2 8/14PIN
74
AT89/83EB5114
4311C–8051–02/08
Status of the Flash Memory
The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY
is set when programming is in progress.
Loading the Column Latches
Any number of data from 1 byte to 128 bytes can be loaded in the column latches. This
provides the capability to program the whole memory by byte, by page or by any number
of bytes in a page.
When programming is launched, an automatic erase of the locations loaded in the col-
umn latches is first performed, then programming is effectively done. Thus no page or
block erase is needed and only the loaded data are programmed in the corresponding
page.
The following procedure is used to load the column latches and is summarized in
Disable interrupt and map the column latch space by setting FPS bit.
Load the DPTR with the address to load.
Load Accumulator register with the data to load.
Execute the MOVX @DPTR, A instruction.
If needed loop the three last instructions until the page is completely loaded.
unmap the column latch and Enable Interrupt
Figure 34. Column Latches Loading Procedure
Note:
The last page address used when loading the column latch is the one used to select the
page programming address.
Column Latches Loading
Data Load
DPTR= Address
ACC= Data
Exec: MOVX @DPTR, A
Last Byte
to load?
Column Latches Mapping
FPS= 1
Data memory Mapping
FPS= 0
Disable IT
EA= 0
Enable IT
EA= 1
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