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| 型號(hào)： | PIC10F204T-I/MC |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 7/94頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 256X12 8DFN |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus |
| 標(biāo)準(zhǔn)包裝： | 3,300 |
| 系列： | PIC® 10F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 3 |
| 程序存儲(chǔ)器容量： | 384B（256 x 12） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 16 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-VFDFN 裸露焊盤(pán) |
| 包裝： | 帶卷 (TR) |
| 配用： | AC164334-ND - MODULE SOCKET FOR 8L 2X3MM DFN AC103003-ND - BOARD DEMO PIC10F CAP TOUCH AC163020-2-ND - ADAPTER PROGRAM PIC10F 2X3 DFN |
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2007 Microchip Technology Inc.
DS41239D-page 13
PIC10F200/202/204/206
3.1
Clocking Scheme/Instruction
Cycle
The clock is internally divided by four to generate four
non-overlapping quadrature clocks, namely Q1, Q2,
Q3 and Q4. Internally, the PC is incremented every Q1
and the instruction is fetched from program memory
and latched into the instruction register in Q4. It is
decoded and executed during the following Q1 through
Q4. The clocks and instruction execution flow is shown
in Figure 3-3 and Example 3-1.
3.2
Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to change (e.g., GOTO), then two cycles
are required to complete the instruction (Example 3-1).
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-3:
CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
PC + 1
PC + 2
Fetch INST (PC)
Execute INST (PC – 1)
Fetch INST (PC + 1)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 1)
Internal
phase
clock
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
1. MOVLW 03H
Fetch 1
Execute 1
2. MOVWF GPIO
Fetch 2
Execute 2
3. CALL
SUB_1
Fetch 3
Execute 3
4. BSF
GPIO, BIT1
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
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