參數(shù)資料
型號(hào): PIC10F322-I/MC
廠商: Microchip Technology
文件頁(yè)數(shù): 141/210頁(yè)
文件大?。?/td> 0K
描述: IC MCU 8BIT 896B FLASH 8DFN
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 150
系列: PIC® 10F
核心處理器: PIC
芯體尺寸: 8-位
速度: 16MHz
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 3
程序存儲(chǔ)器容量: 896B(512 x 14)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-VFDFN 裸露焊盤
包裝: 托盤
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PIC10(L)F320/322
DS41585A-page 36
Preliminary
2011 Microchip Technology Inc.
5.3
Low-Power Brown-out Reset
(LPBOR)
The Low-Power Brown-Out Reset (LPBOR) is an
essential part of the Reset subsystem. Refer to
Figure 5-1 to see how the BOR interacts with other
modules.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the LPBOR.
Refer to Register 5-2.
5.3.1
ENABLING LPBOR
The LPBOR is controlled by the LPBOR bit of
Configuration Word. When the device is erased, the
LPBOR module defaults to disabled.
5.3.1.1
LPBOR Module Output
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR mod-
ule to provide the generic BOR signal which goes to
the PCON register and to the power control block.
5.4
MCLR
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE and the LVP bit of Configuration Word (Table 5-
5.4.1
MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
5.4.2
MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control.
5.5
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 8.0
for more information.
5.6
Programming Mode ICSP Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
5.7
Power-Up Timer
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
The Power-up Timer is controlled by the PWRTE bit of
Configuration Word.
5.8
Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1.
Power-up Timer runs to completion (if enabled).
2.
MCLR must be released (if enabled).
The total time-out will vary based on oscillator configu-
ration and Power-up Timer configuration. See
for more informa-
tion.
The Power-up Timer runs independently of MCLR
Reset. If MCLR is kept low long enough, the Power-up
Timer will expire. Upon bringing MCLR high, the device
will begin execution immediately (see Figure 5-3). This
is useful for testing purposes or to synchronize more
than one device operating in parallel.
TABLE 5-2:
MCLR CONFIGURATION
MCLRE
LVP
MCLR
00
Disabled
10
Enabled
x1
Enabled
Note:
A Reset does not drive the MCLR pin low.
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