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參數(shù)資料
| 型號(hào)： | PIC12C509AT-04I/MF |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 54/113頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 1KX12 8-DFN |
| 標(biāo)準(zhǔn)包裝： | 3,300 |
| 系列： | PIC® 12C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲(chǔ)器容量： | 1.5KB（1K x 12） |
| 程序存儲(chǔ)器類型： | OTP |
| RAM 容量： | 41 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-VDFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
| 配用： | AC164324-ND - MODULE SKT FOR MPLAB 8DFN/16QFN XLT08DFN2-ND - SOCKET TRANSITION ICE 14DIP/8DFN XLT08DFN-ND - SOCKET TRANSITION ICE 8DFN AC164032-ND - ADAPTER PICSTART PLUS 8DFN/DIP AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC |
| 其它名稱： | PIC12C509AT04I/MF |
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1999 Microchip Technology Inc.
DS40139E-page 45
PIC12C5XX
8.9
Power-Down Mode (SLEEP)
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
8.9.1
SLEEP
The Power-Down mode is entered by executing a
SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low, or hi-impedance).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR pin low.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the GP3/
MCLR/VPP pin must be at a logic high level (VIHMC) if
MCLR is enabled.
8.9.2
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
An external reset input on GP3/MCLR/VPP pin,
when configured as MCLR.
2.
A Watchdog Timer time-out reset (if WDT was
enabled).
3.
A change on input pin GP0, GP1, or GP3/
MCLR/VPP
when
wake-up
on
change
is
enabled.
These events cause a device reset. The TO, PD, and
GPWUF bits can be used to determine the cause of
device reset. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The GPWUF bit indicates a change in state while in
SLEEP at pins GP0, GP1, or GP3 (since the last time
there was a file or bit operation on GP port).
The WDT is cleared when the device wakes from
sleep, regardless of the wake-up source.
Caution: Right before entering SLEEP, read the
input pins. When in SLEEP, wake up
occurs when the values at the pins change
from the state they were in at the last
reading. If a wake-up on change occurs
and
the
pins
are
not
read
before
reentering SLEEP, a wake up will occur
immediately even if no pins change while
in SLEEP mode.
8.10
Program Verification/Code Protection
If the code protection bit has not been programmed,
the on-chip program memory can be read out for
verification purposes.
The first 64 locations can be read by the PIC12C5XX
regardless of the code protection bit setting.
The last memory location cannot be read if code pro-
tection is enabled on the PIC12C508/509.
The last memory location can be read regardless of the
code protection bit setting on the PIC12C508A/509A/
CR509A/CE518/CE519.
8.11
ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other code-
identification
numbers.
These
locations
are
not
accessible during normal execution but are readable
and writable during program/verify.
Use only the lower 4 bits of the ID locations and
always program the upper 8 bits as ’0’s.
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