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參數資料
| 型號： | PIC12C509T-04E/SM |
| 廠商： | Microchip Technology |
| 文件頁數： | 39/113頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 1KX12 8-SOIJ |
| 產品培訓模塊： | Asynchronous Stimulus |
| 標準包裝： | 2,100 |
| 系列： | PIC® 12C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設備： | POR，WDT |
| 輸入/輸出數： | 5 |
| 程序存儲器容量： | 1.5KB（1K x 12） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 41 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 8-SOIC（0.209"，5.30mm 寬） |
| 包裝： | 帶卷 (TR) |
| 配用： | XLT08SO-1-ND - SOCKET TRANSITION 8SOIC 150/208 AC164312-ND - MODULE SKT FOR PM3 16SOIC 309-1048-ND - ADAPTER 8-SOIC TO 8-DIP 309-1047-ND - ADAPTER 8-SOIC TO 8-DIP |
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1999 Microchip Technology Inc.
DS40139E-page 31
PIC12C5XX
7.0.2
SERIAL CLOCK
This SCL input is used to synchronize the data transfer
from and to the device.
7.1
BUS CHARACTERISTICS
The following bus protocol is to be used with the
EEPROM data memory.
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as a
START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 7-3).
7.1.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
7.1.2
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
7.1.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
7.1.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
7.1.5
ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse.
Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 7-4).
Note:
Acknowledge bits are not generated if an
internal programming cycle is in progress.
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| PIC12C509T-04I/SM | 功能描述:8位微控制器 -MCU 1.5KB 41 RAM 6 I/O 4MHz Ind Temp SOIC8 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC12C509T-04I/SN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| PIC12C5X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| PIC12C5XX | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8-Pin, 8-Bit CMOS Microcontrollers |
| PIC12C67 | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:EPROM Memory Programming Specification |
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