參數(shù)資料
型號: PIC12C671-10E/SM
廠商: Microchip Technology
文件頁數(shù): 58/129頁
文件大?。?/td> 0K
描述: IC MCU OTP 1KX14 A/D 8-SOIJ
產品培訓模塊: Asynchronous Stimulus
標準包裝: 90
系列: PIC® 12C
核心處理器: PIC
芯體尺寸: 8-位
速度: 10MHz
外圍設備: POR,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 1.75KB(1K x 14)
程序存儲器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 4x8b
振蕩器型: 內部
工作溫度: -40°C ~ 125°C
封裝/外殼: 8-SOIC(0.209",5.30mm 寬)
包裝: 管件
配用: AC164312-ND - MODULE SKT FOR PM3 16SOIC
309-1048-ND - ADAPTER 8-SOIC TO 8-DIP
309-1047-ND - ADAPTER 8-SOIC TO 8-DIP
PIC12C67X
DS30561B-page 34
1999 Microchip Technology Inc.
6.1.5
ACKNOWLEDGE
The EEPROM, when addressed, will generate an
acknowledge after the reception of each byte. The pro-
cessor must generate an extra clock pulse which is
associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. The processor must signal an end of data to
the EEPROM by not generating an acknowledge bit on
the last byte that has been clocked out of the EEPROM.
In this case, the EEPROM must leave the data line
HIGH to enable the processor to generate the STOP
condition (Figure 6-4).
FIGURE 6-1:
BLOCK DIAGRAM OF GPIO6 (SDA LINE)
FIGURE 6-2:
BLOCK DIAGRAM OF GPIO7 (SCL LINE)
Note:
Acknowledge bits are not generated if an
internal programming cycle is in progress.
EN
D
EN
QD
CK
Reset
CK
Q
Data Bus
Write
Output Latch
To EEPROM SDA
Schmitt Trigger
ltchpin
Input Latch
Read
VDD
Pad
GPIO
P
D
EN
QD
CK
Q
Data Bus
Write
To EEPROM SCL
ltchpin
Read
VDD
Pad
Schmitt Trigger
GPIO
P
N
Output Latch
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