參數(shù)資料
型號: PIC12F509-I/MC
廠商: Microchip Technology
文件頁數(shù): 32/44頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 1024X12 8DFN
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 150
系列: PIC® 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 1.5KB(1K x 12)
程序存儲器類型: 閃存
RAM 容量: 41 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-VFDFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 637 (CN2011-ZH PDF)
配用: AC164334-ND - MODULE SOCKET FOR 8L 2X3MM DFN
AC162059-ND - HEADER INTRFC MPLAB ICD2 8/14PIN
DVA12XP080-ND - ADAPTER DEVICE FOR MPLAB-ICE
38
6062LS–ATARM–23-Mar-09
AT91SAM9261
10.13 USB
USB Host Port:
– Compliance with Open HCI Rev 1.0 specification
– Compliance with USB V2.0 Full-speed and Low-speed Specification
– Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices
– Root hub integrated with two downstream USB ports
– Two embedded USB transceivers
– No overcurrent detection
– Supports power management
– Operates as a master on the Bus Matrix
USB Device Port:
– USB V2.0 full-speed compliant, 12 Mbits per second
– Embedded USB V2.0 full-speed transceiver
– Embedded dual-port RAM for endpoints
– Suspend/Resume logic
– Ping-pong mode (two memory banks) for isochronous and bulk endpoints
– Six general-purpose endpoints:
Endpoint 0: 8 bytes, no ping-pong mode
Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode
Endpoint 3: 64 bytes, no ping-pong mode
Endpoint 4, Endpoint 5: 256 bytes, ping-pong mode
Embedded pad pull-up configurable via USB_PUCR Register located in the MATRIX user
interface
10.14 LCD Controller
Single and Dual scan color and monochrome passive STN LCD panels supported
Single scan active TFT LCD panels supported.
4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported
Up to 24-bit single scan TFT interfaces supported
Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays
1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN
1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN
1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT
Single clock domain architecture
Resolution supported up to 2048 x 2048
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