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參數(shù)資料
| 型號： | PIC12F629T-I/MF |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 35/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU CMOS 8BIT 1K FLASH 8-DFN |
| 產(chǎn)品培訓模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標準包裝： | 3,300 |
| 系列： | PIC® 12F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 外圍設備： | POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲器容量： | 1.75KB（1K x 14） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 128 x 8 |
| RAM 容量： | 64 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-VDFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
| 配用： | AC164324-ND - MODULE SKT FOR MPLAB 8DFN/16QFN XLT08DFN2-ND - SOCKET TRANSITION ICE 14DIP/8DFN XLT08DFN-ND - SOCKET TRANSITION ICE 8DFN AC164032-ND - ADAPTER PICSTART PLUS 8DFN/DIP AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC |
| 其它名稱： | PIC12F629-I/MFTR PIC12F629T-I/MFTR PIC12F629T-I/MFTR-ND |
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9
AT89S53
0787E–MICRO–3/06
Data Memory - RAM
The AT89S53 implements 256 bytes of RAM. The upper
128 bytes of RAM occupy a parallel space to the Special
Function Registers. That means the upper 128 bytes have
the same addresses as the SFR space but are physically
separate from SFR space.
When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions that use direct
addressing access SFR space.
For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing instruction, where R0 contains 0A0H, accesses
the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail-
able as stack space.
Programmable Watchdog Timer
The programmable Watchdog Timer (WDT) operates from
an independent oscillator. The prescaler bits, PS0, PS1
and PS2 in SFR WCON are used to set the period of the
Watchdog Timer from 16 ms to 2048 ms. The available
timer periods are shown in the following table and the
actual timer periods (at V
CC = 5V) are within ±30% of the
nominal.
The WDT is disabled by Power-on Reset and during
Power-down. It is enabled by setting the WDTEN bit in SFR
WCON (address = 96H). The WDT is reset by setting the
WDTRST bit in WCON. When the WDT times out without
being reset or disabled, an internal RST pulse is generated
to reset the CPU.
Timer 0 and 1
Timer 0 and Timer 1 in the AT89S53 operate the same way
as Timer 0 and Timer 1 in the AT89C51, AT89C52 and
AT89C55. For further information, see the October 1995
Microcontroller Data Book, page 2-45, section titled,
“Timer/Counters.”
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either
a timer or an event counter. The type of operation is
selected by bit C/T2 in the SFR T2CON (shown in Table 2).
Timer 2 has three operating modes: capture, auto-reload
(up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 8.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the
Timer function, the TL2 register is incremented every
machine cycle. Since a machine cycle consists of 12 oscil-
lator periods, the count rate is 1/12 of the oscillator
frequency.
In the Counter function, the register is incremented in
response to a 1-to-0 transition at its corresponding external
input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples
show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in which
the transition was detected. Since two machine cycles (24
oscillator periods) are required to recognize a 1-to-0 transi-
tion, the maximum count rate is 1/24 of the oscillator
frequency. To ensure that a given level is sampled at least
once before it changes, the level should be held for at least
one full machine cycle.
Table 7. Watchdog Timer Period Selection
WDT Prescaler Bits
Period (nominal)
PS2
PS1
PS0
0
16 ms
0
1
32 ms
0
1
0
64 ms
0
1
128 ms
1
0
256 ms
1
0
1
512 ms
1
0
1024 ms
1
2048 ms
Table 8. Timer 2 Operating Modes
RCLK + TCLK
CP/RL2
TR2
MODE
0
1
16-bit Auto-Reload
0
1
16-bit Capture
1
X
1
Baud Rate Generator
X
0
(Off)
Table 7. Watchdog Timer Period Selection
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