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參數(shù)資料
| 型號： | PIC12F675T-I/SN |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 10/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU CMOS 1K FLASH W/AD 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 3,300 |
| 系列： | PIC® 12F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲器容量： | 1.75KB（1K x 14） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 128 x 8 |
| RAM 容量： | 64 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | PIC12F675-I/SNTR PIC12F675-I/SNTR-ND PIC12F675T-I/SN-ND PIC12F675T-I/SNTR Q1324216 |
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AT89S53
0787E–MICRO–3/06
18
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware
reset, the device normally resumes program execution
from where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when idle mode is termi-
nated by a reset, the instruction following the one that
invokes idle mode should not write to a port pin or to exter-
nal memory.
Power-down Mode
In the power-down mode, the oscillator is stopped and the
instruction that invokes power-down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power-down mode is
terminated. Exit from power-down can be initiated either by
a hardware reset or by an enabled external interrupt. Reset
redefines the SFRs but does not change the on-chip RAM.
The reset should not be activated before V
CC is restored to
its normal operating level and must be held active long
enough to allow the oscillator to restart and stabilize.
To exit power-down via an interrupt, the external interrupt
must be enabled as level sensitive before entering power-
down. The interrupt service routine starts at 16 ms (nomi-
nal) after the enabled interrupt pin is activated.
Program Memory Lock Bits
The AT89S53 has three lock bits that can be left unpro-
grammed (U) or can be programmed (P) to obtain the
additional features listed in the following table.
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
value and holds that value until reset is activated. The
latched value of EA must agree with the current logic level
at that pin in order for the device to function properly.
Once programmed, the lock bits can only be unpro-
grammed with the Chip Erase operations in either the
parallel or serial modes.
Notes:
1. U = Unprogrammed
2. P = Programmed
Status of External Pins During Idle and Power-down Modes
Mode
Program Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Internal
1
Data
Idle
External
1
Float
Data
Address
Data
Power-down
Internal
0
Data
Power-down
External
0
Float
Data
Lock Bit Protection Modes(1)(2)
Program Lock Bits
Protection Type
LB1
LB2
LB3
1
U
No internal memory lock feature.
2
P
U
MOVC instructions executed from external program memory are disabled from fetching code bytes
from internal memory. EA is sampled and latched on reset and further programming of the Flash
memory (parallel or serial mode) is disabled.
3
P
U
Same as Mode 2, but parallel or serial verify are also disabled.
4
P
Same as Mode 3, but external execution is also disabled.
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