參數(shù)資料
型號: PIC12F683T-E/SN
廠商: Microchip Technology
文件頁數(shù): 134/176頁
文件大小: 0K
描述: IC MCU FLASH 2KX14 8SOIC
產(chǎn)品培訓模塊: Asynchronous Stimulus
Digi-Key 應用說明: AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
標準包裝: 3,300
系列: PIC® 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 帶卷 (TR)
配用: AC162058-ND - HEADER MPLAB ICD2 FOR PIC12F683
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
PIC12F683
DS41211D-page 58
2007 Microchip Technology Inc.
8.11
Comparator Voltage Reference
The Comparator Voltage Reference module provides
an internally generated voltage reference for the
comparators. The following features are available:
Independent from Comparator operation
Two 16-level voltage ranges
Output clamped to VSS
Ratiometric with VDD
The VRCON register (Register 8-3) controls the
Voltage Reference module shown in Figure 8-7.
8.11.1
INDEPENDENT OPERATION
The comparator voltage reference is independent of
the comparator configuration. Setting the VREN bit of
the VRCON register will enable the voltage reference.
8.11.2
OUTPUT VOLTAGE SELECTION
The
CVREF voltage reference has 2 ranges with 16
voltage levels in each range. Range selection is
controlled by the VRR bit of the VRCON register. The
16 levels are set with the VR<3:0> bits of the VRCON
register.
The CVREF output voltage is determined by the following
equations:
EQUATION 8-1:
CVREF OUTPUT VOLTAGE
The full range of VSS to VDD cannot be realized due to
the construction of the module. See Figure 8-1.
8.11.3
OUTPUT CLAMPED TO VSS
The CVREF output voltage can be set to Vss with no
power consumption by configuring VRCON as follows:
VREN = 0
VRR = 1
VR<3:0> = 0000
This allows the comparator to detect a zero-crossing
while not consuming additional CVREF module current.
8.11.4
OUTPUT RATIOMETRIC TO VDD
The comparator voltage reference is VDD derived and
therefore, the CVREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 15.0
VRR
1 (low range):
=
VRR
0 (high range):
=
CVREF
(VDD/4) +
=
CVREF
(VR<3:0>/24)
VDD
×
=
(VR<3:0>
VDD/32)
×
REGISTER 8-3:
VRCON: VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
R/W-0
VREN
—VRR
VR3
VR2
VR1
VR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
VREN: CVREF Enable bit
1
= CVREF circuit powered on
0
= CVREF circuit powered down, no IDD drain and CVREF = VSS.
bit 6
Unimplemented: Read as ‘0’
bit 5
VRR: CVREF Range Selection bit
1
= Low range
0
= High range
bit 4
Unimplemented: Read as ‘0’
bit 3-0
VR<3:0>: CVREF Value Selection 0
≤ VR<3:0> ≤ 15
When VRR = 1: CVREF = (VR<3:0>/24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD
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