參數(shù)資料
型號(hào): PIC14000-20I/SS
廠商: Microchip Technology
文件頁(yè)數(shù): 140/153頁(yè)
文件大?。?/td> 0K
描述: IC MCU OTP 4KX14 A/D 28SSOP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 47
系列: PIC® 14
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C
外圍設(shè)備: POR,溫度傳感器,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 7KB(4K x 14)
程序存儲(chǔ)器類型: OTP
RAM 容量: 192 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: 斜率 A/D
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
包裝: 管件
配用: 309-1025-ND - ADAPTER 28-SSOP TO 28-DIP
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1996 Microchip Technology Inc.
Preliminary
DS40122B-page 87
PIC14000
10.8.1
SLEEP MODE
The SLEEP mode is entered by executing a SLEEP
instruction.
If SLEEP mode is enabled, the WDT will be cleared but
keep running. The PD bit in the STATUS register is
cleared, the TO bit is set, and on-chip oscillators are
shut off, except the WDT RC oscillator, which continues
to run. The I/O ports maintain the status they had
before the SLEEP command was executed (driving
high, low, or high-impedance).
It is an option while in SLEEP mode to leave the
on-chip oscillator running. This option allows an A/D
conversion to continue while the CPU is in SLEEP
mode. The CPU clocks are stopped in this condition to
preserve power. The operation of the on-chip oscillator
during
SLEEP
is
controlled
by
OSCOFF
(SLPCON<3>). Clearing this bit to ‘0’ allows the oscil-
lator to continue to run. This bit is only active in SLEEP
mode.
For lowest power consumption in this mode, all I/O pins
should be either at VDD or VSS with no external circuitry
drawing current from the I/O pin. I/O pins that are
high-impedance inputs should be pulled high or low
externally to avoid leakage currents caused by oating
inputs. The MCLR pin must be at a logic high level
(VIH). The contribution from any on-chip pull-up
resistors should be considered.
10.8.2
WAKE-UP FROM SLEEP
The PIC14000 can wake up from SLEEP through one
of the following events:
1.
External reset input on MCLR pin
2.
Watchdog Timer time-out (if WDT is enabled)
3.
Interrupt from OSC1/PBTN pin
4.
RC<7:4> port change
5.
I2C (serial port) start/stop bit detect interrupt.
6.
Wake-up on programmable reference compara-
tor interrupt.
7.
A/D conversion complete (comparator trip) inter-
rupt.
8.
A/D timer overow interrupt.
An external reset on MCLR pin causes a device reset.
The
other
wake-up
events
are
considered
a
continuation of program execution. The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
a wake-up).
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set. Wake-up occurs
regardless of the state of bit GIE. If bit GIE is clear, the
device continues execution at the instruction after the
SLEEP
instruction. If bit GIE is set, the device executes
the instruction after the SLEEP instruction and then
branches to the interrupt address (0004h). In cases
where the execution of the instruction following SLEEP
is not desirable, the user should have a NOP after the
SLEEP
instruction.
The WDT is cleared when the device wakes-up from
sleep, regardless of the source of wake-up.
Note:
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its
interrupt
enable
bit
and
the
corresponding interrupt ag bits set, the
device will immediately wake from SLEEP.
10.8.3
HIBERNATE MODE
HIBERNATE mode is an extension of SLEEP mode
with the following additions.
WDT is forced off
Weak pull-ups on RC<5:0> are disabled
Some input buffers are gated-off (refer to
Section 5.0)
The HIBERNATE mode is entered by executing a
SLEEP
instruction with HIBEN (SLPCON<7>) bit set.
The PIC14000 wakes up from HIBERNATE mode via
all the same mechanisms as SLEEP mode, except for
WDT time-out. HIBERNATE mode allows power con-
sumption to be reduced to a minimum.
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