Once the I2
參數(shù)資料
型號(hào)： PIC14000T-04/SS
廠商： Microchip Technology
文件頁(yè)數(shù)： 100/153頁(yè)
文件大?。?/td> 0K
描述： IC MCU OTP 4KX14 A/D 28SSOP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 2,100
系列： PIC® 14
核心處理器： PIC
芯體尺寸： 8-位
速度： 4MHz
連通性： I²C
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 20
程序存儲(chǔ)器容量： 7KB（4K x 14）
程序存儲(chǔ)器類(lèi)型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器： 斜率 A/D
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
包裝： 帶卷 (TR)
配用： 309-1025-ND - ADAPTER 28-SSOP TO 28-DIP
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PIC14000
DS40122B-page 50
Preliminary
1996 Microchip Technology Inc.
7.5.1.1
ADDRESSING
Once the I2C module has been enabled, the I2C waits
for a START to occur. Following the START, the 8-bits
are shifted into the I2CSR. All incoming bits are
sampled with the rising edge of the clock (SCL) line.
The I2CSR<7:1> is compared to the I2CADD register.
The address is compared on the falling edge of the
eighth clock (SCL) pulse. If the addresses match, and
the BF and I2COV bits are clear, the following things
happen:
I2CSR loaded into I2CBUF
Buffer Full (BF) bit is set
ACK pulse is generated
I2C Interrupt Flag (I2CIF) is set (interrupt is
generated if enabled (I2CIE set) on falling edge of
ninth SCL pulse.
In 10-bit address mode, two address bytes need to be
received by the slave (Figure 7-5). The ve most
signicant bits (MSbs) of the rst address byte specify
if this is a 10-bit address. The R/W bit (bit 0) must
specify a write, so the slave device will received the
second address byte. For a 10-bit address the rst byte
would equal ‘1 1 1 1 0 A9 A8 0’, where A9 and A8 are
the two MSbs of the address. The sequence of events
for 10-bit address are as follows, with steps 7-9 for
slave-transmitter:
1.
Receive rst (high) byte of address (I2CIF, BF
and UA are set).
2.
Update I2CADD with second (low) byte of
address (clears UA and releases SCL line).
3.
Read I2CBUF (clears BF) and clear I2CIF.
4.
Receive second (low) byte of address (I2CIF, BF
and UA are set).
5.
Update I2CADD with rst (high) byte of address
(clears UA, if match releases SCL line).
6.
Read I2CBUF (clears BF) and clear I2CIF
7.
Receive Repeated START.
8.
Receive rst (high) byte of address (I2CIF and
BF are set).
9.
Read I2CBUF (clears BF) and clear I2CIF.
7.5.1.2
RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the I2CSTAT
register is cleared. The received address is loaded into
the I2CBUF.
When the address byte overow condition exists then
no acknowledge (ACK) pulse is given. An overow
condition is dened as either the BF bit (I2CSTAT<0>)
is
set
or
the
I2COV
bit
(I2CCON<6>)
is
set
An I2CIF interrupt is generated for each data transfer
byte. The I2CIF bit must be cleared in software, and the
I2CSTAT register is used to determine the status of the
byte. In master mode with slave enabled, three inter-
rupt sources are possible. Reading BF, P and S will
indicate the source of the interrupt.
Caution:
BF is set after receipt of eight bits and auto-
matically cleared after the I2CBUF is read.
However, the ag is not actually cleared
until receipt of the acknowledge pulse. Oth-
erwise extra reads appear to be valid.
FIGURE 7-14: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P
9
8
7
6
5
D0
D1
D2
D3
D4
D5
D6
D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL
12
3
4
5
6
7
8
9
12
3
4
56
7
89
12
3
4
Bus Master
terminates
transfer
I2COV is set
because I2CBUF is
Cleared in software
I2CBUF is read
ACK
Receiving Data
D0
D1
D2
D3
D4
D5
D6
D7
ACK
Receiving Address
I2CIF (PIR1<3>)
BF (I2CSTAT<0>)
I2COV (I2CCON<6>)
ACK
R/W=0
still full. ACK is not sent.
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